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I'm using the Keil MCBSTM32F400 development board and I'd like to start using the external SRAM.
From the user's guide the SRAM uses the following pins and is at the following location: SRAM FSMC_NE3 / PG10 0x68000000 - 0x681FFFFF
I'm having trouble accessing the memory. When trying to write, nothing happens and when reading back I always get 0xFF.
Does anyone have an example of setting up the FSMC for the Keil development board to use its external SRAM?
Is there a Keil example application that shows how to use the memory?
What I've tried so far:
In the standard system_stm32f4xx.c file, I enabled the external memory by defining DATA_IN_ExtSRAM (uncommenting).
In the SystemInit_ExtMemCtl() function I commented out three lines where they were directly configuring the FSMC_Bank1 timing and control registers; uncommented the FSMC_NORSRAMInitStructure; changed FSMC_Bank1_NORSRAM2 to FSMC_Bank1_NORSRAM3; called teh FSMC_NORSRAMInit() function with the structure; and finally added a call to FSMC_NORSRAMCmd() to enable.
I did not change any of the GPIO alternate function setup from what is in the standard system file.
I have not looked into the timing settings for the SRAM on the Keil board vs. the timing for the G_EVAL board external SRAM to see if they're different enough to change.
Any help would be greatly appreciated.
Chris Kern, You need to adjust the memory as it was stated a few posts above and added a line from my previous post. In this case would not need to use Write_ and Read_ Buffer
In my startup_stm32f4xx.s file I change
__initial_sp EQU 0x20000000+Stack_Size ;
In my system_stm32f4xx.c file: 1) uncomment
#define DATA_IN_ExtSRAM
2) change
#ifdef DATA_IN_ExtSRAM /** * @brief Setup the external memory controller. * Called in startup_stm32f4xx.s before jump to main. * This function configures the external SRAM mounted on STM324xG_EVAL board * This SRAM will be used as program data memory (including heap and stack). * @param None * @retval None */ void SystemInit_ExtMemCtl(void) { /*-- GPIOs Configuration -----------------------------------------------------*/ /* +-------------------+--------------------+------------------+------------------+ + SRAM pins assignment + +-------------------+--------------------+------------------+------------------+ | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | | PD4 <-> FSMC_NOE | PE3 <-> FSMC_A19 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | | PD5 <-> FSMC_NWE | PE4 <-> FSMC_A20 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | | PD8 <-> FSMC_D13 | PE7 <-> FSMC_D4 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | | PD9 <-> FSMC_D14 | PE8 <-> FSMC_D5 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | | PD10 <-> FSMC_D15 | PE9 <-> FSMC_D6 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 OLD EXAMPLE| | PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7 | PF13 <-> FSMC_A7 |-PG10 <-> FSMC_NE3 For Keil board+ | PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8 | PF14 <-> FSMC_A8 | | PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9 | PF15 <-> FSMC_A9 | | PD14 <-> FSMC_D0 | PE13 <-> FSMC_D10 |------------------+ | PD15 <-> FSMC_D1 | PE14 <-> FSMC_D11 | | | PE15 <-> FSMC_D12 | +-------------------+--------------------+ */ FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; FSMC_NORSRAMTimingInitTypeDef p; /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ RCC->AHB1ENR = 0x00000078; /* Connect PDx pins to FSMC Alternate function */ GPIOD->AFR[0] = 0x00cc00cc; GPIOD->AFR[1] = 0xcc0ccccc; /* Configure PDx pins in Alternate function mode */ GPIOD->MODER = 0xaaaa0a0a; /* Configure PDx pins speed to 100 MHz */ GPIOD->OSPEEDR = 0xffff0f0f; /* Configure PDx pins Output type to push-pull */ GPIOD->OTYPER = 0x00000000; /* No pull-up, pull-down for PDx pins */ GPIOD->PUPDR = 0x00000000; /* Connect PEx pins to FSMC Alternate function */ GPIOE->AFR[0] = 0xc00cc0cc; GPIOE->AFR[1] = 0xcccccccc; /* Configure PEx pins in Alternate function mode */ GPIOE->MODER = 0xaaaa828a; /* Configure PEx pins speed to 100 MHz */ GPIOE->OSPEEDR = 0xffffc3cf; /* Configure PEx pins Output type to push-pull */ GPIOE->OTYPER = 0x00000000; /* No pull-up, pull-down for PEx pins */ GPIOE->PUPDR = 0x00000000; /* Connect PFx pins to FSMC Alternate function */ GPIOF->AFR[0] = 0x00cccccc; GPIOF->AFR[1] = 0xcccc0000; /* Configure PFx pins in Alternate function mode */ GPIOF->MODER = 0xaa000aaa; /* Configure PFx pins speed to 100 MHz */ GPIOF->OSPEEDR = 0xff000fff; /* Configure PFx pins Output type to push-pull */ GPIOF->OTYPER = 0x00000000; /* No pull-up, pull-down for PFx pins */ GPIOF->PUPDR = 0x00000000; /* Connect PGx pins to FSMC Alternate function */ GPIOG->AFR[0] = 0x00cccccc; GPIOG->AFR[1] = 0x00000c00; //was 0x000000c0 /* Configure PGx pins in Alternate function mode */ GPIOG->MODER = 0x00200aaa; //was 0x00080aaa /* Configure PGx pins speed to 100 MHz */ GPIOG->OSPEEDR = 0x00300fff; //was 0x000c0fff /* Configure PGx pins Output type to push-pull */ GPIOG->OTYPER = 0x00000000; /* No pull-up, pull-down for PGx pins */ GPIOG->PUPDR = 0x00000000; /*-- FSMC Configuration ------------------------------------------------------*/ /* Enable the FSMC interface clock */ //RCC->AHB3ENR |= (1UL << 0); /* enable FSMC clock */ RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); /* Configure and enable Bank1_SRAM2 */ //original example // FSMC_Bank1->BTCR[2] = 0x00001015; // FSMC_Bank1->BTCR[3] = 0x00010603; // FSMC_Bank1E->BWTR[2] = 0x0fffffff; /* Bank1_SRAM3 is configured as follow: */ p.FSMC_AddressSetupTime = 3; p.FSMC_AddressHoldTime = 0; p.FSMC_DataSetupTime = 6; p.FSMC_BusTurnAroundDuration = 1; p.FSMC_CLKDivision = 0; p.FSMC_DataLatency = 0; p.FSMC_AccessMode = FSMC_AccessMode_A; //FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3; //For Keil FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; //FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; //For Keil FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE); }
And change Target options like this gyazo.com/5e7bd147689cd9d29ea6b553c2fcc1f5
This work for me.
Hi Toff,
TY for your response.
I did lots of experimental work and in 2 of 3 projects i could not manage to work your solution. One of them is my own project with quite huge stack size, the other is Keils Http_demo.
But in Blinky example of Keil, its working like a charm.
In my opinion its all about;
__initial_sp EQU 0x20000000+Stack_Size
what did you intent to achieve with this code line?
It seems i need to move my stack pointer also somewhere, but for now i donot know where to move and i donot have any idea, yet.