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Is this a bug of Keil in Cortex-M3

When we choose STM32F103 everything is normal, when choose STM32F105, "build target' is still no error, but when debug, 'error 65: access violation at 0x40021000: no 'read' permission'. 0x40021000 is the register of RCC, and no different between the STM32F103 and the STM32F105. Is this a bug of Keil? Anybody can help?

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  • This is the example program of Keil in the 'system_stm32f10x.c' I have made the define of STM32F10X_CL, but when debug, the error 65 occur.

    void SystemInit (void)
    { /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ /* Set HSION bit */
    RCC->CR |= (uint32_t)0x00000001;

    /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */

    #ifndef STM32F10X_CL RCC->CFGR &= (uint32_t)0xF8FF0000;
    #else RCC->CFGR &= (uint32_t)0xF0FF0000;
    #endif /* STM32F10X_CL */

    /* Reset HSEON, CSSON and PLLON bits */

    RCC->CR &= (uint32_t)0xFEF6FFFF;

    /* Reset HSEBYP bit */

    RCC->CR &= (uint32_t)0xFFFBFFFF;

    /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */

    RCC->CFGR &= (uint32_t)0xFF80FFFF;

    #ifdef STM32F10X_CL /* Reset PLL2ON and PLL3ON bits */

    RCC->CR &= (uint32_t)0xEBFFFFFF;

    /* Disable all interrupts and clear pending bits */

    RCC->CIR = 0x00FF0000;

    /* Reset CFGR2 register */

    RCC->CFGR2 = 0x00000000;

    #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) /* Disable all interrupts and clear pending bits */

    RCC->CIR = 0x009F0000;

    /* Reset CFGR2 register */

    RCC->CFGR2 = 0x00000000;
    #else /* Disable all interrupts and clear pending bits */

    RCC->CIR = 0x009F0000;
    #endif /* STM32F10X_CL */

    #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) #ifdef DATA_IN_ExtSRAM SystemInit_ExtMemCtl(); #endif /* DATA_IN_ExtSRAM */
    #endif

    /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ /* Configure the Flash Latency cycles and enable prefetch buffer */

    SetSysClock();

    #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
    #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
    #endif
    }

Reply
  • This is the example program of Keil in the 'system_stm32f10x.c' I have made the define of STM32F10X_CL, but when debug, the error 65 occur.

    void SystemInit (void)
    { /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ /* Set HSION bit */
    RCC->CR |= (uint32_t)0x00000001;

    /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */

    #ifndef STM32F10X_CL RCC->CFGR &= (uint32_t)0xF8FF0000;
    #else RCC->CFGR &= (uint32_t)0xF0FF0000;
    #endif /* STM32F10X_CL */

    /* Reset HSEON, CSSON and PLLON bits */

    RCC->CR &= (uint32_t)0xFEF6FFFF;

    /* Reset HSEBYP bit */

    RCC->CR &= (uint32_t)0xFFFBFFFF;

    /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */

    RCC->CFGR &= (uint32_t)0xFF80FFFF;

    #ifdef STM32F10X_CL /* Reset PLL2ON and PLL3ON bits */

    RCC->CR &= (uint32_t)0xEBFFFFFF;

    /* Disable all interrupts and clear pending bits */

    RCC->CIR = 0x00FF0000;

    /* Reset CFGR2 register */

    RCC->CFGR2 = 0x00000000;

    #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) /* Disable all interrupts and clear pending bits */

    RCC->CIR = 0x009F0000;

    /* Reset CFGR2 register */

    RCC->CFGR2 = 0x00000000;
    #else /* Disable all interrupts and clear pending bits */

    RCC->CIR = 0x009F0000;
    #endif /* STM32F10X_CL */

    #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) #ifdef DATA_IN_ExtSRAM SystemInit_ExtMemCtl(); #endif /* DATA_IN_ExtSRAM */
    #endif

    /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ /* Configure the Flash Latency cycles and enable prefetch buffer */

    SetSysClock();

    #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
    #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
    #endif
    }

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