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Bug in simulation of virtual registors and their true port values

Hello!

Im using PK51 v9.05 for simulation poresess of external signal input.
Wrote script where time depended signal function change PORT3 pin state:

...
swatch (0.0250);
PORT3 ^= (1<<2);
swatch (0.0015);}
PORT3 |= (1<<2);
...

In analyzer window - I can see that correct signal, as PORT3 value,
but in program, when virtual PORT3, for ex. shows 0xFB value,
the real P3 always gives 0xFF .. Why, what did I wrong ?

PS: Strange, but some raroe time P3=PORT3 finally, not all time.

^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

PPS: Beside, I marked, when Logic Analyzer is active and collect plenty of trace data, pressing of "Reset CPU" button totally crash Keil (v4.22) IDE. Annoying bug really

Parents
  • Ok folks, am not a begginer and I good knowledge of architecture the c51/52.

    If support would be interesting I could send them demo project, that illustrate both of that bugs. But smth tells me, that they have been reported or just know about that problem.

    Regars.

Reply
  • Ok folks, am not a begginer and I good knowledge of architecture the c51/52.

    If support would be interesting I could send them demo project, that illustrate both of that bugs. But smth tells me, that they have been reported or just know about that problem.

    Regars.

Children