LPC23xx SSP slave Mode

But you could have connected that single master pin to every slave, in case you don't need two-way communication.

Or if you do need data from slaves, you use an additional gate and a couple of GPIO pins to specify an address, making sure that only one slave gets the enable signal.

You are basically building an elevator without sensors for floor position and top/bottom position. Then you let the elevator motor just count time to try to figure out if it is getting close to third or fourth floor, totally without feedback for error correction.

A SPI slave can work with constantly enabled slave select. But one single pulse extra or lost means it will be one bit off until you reset the controller or you deactivate/reactivate the slave-select signal. What mechanics do you have to get your slaves to know when to reset the SPI controller, since you obviously can't toggle the slave select input?

Where did you find the recommendation to use:

here i am using for master CPOL=0,CPHA=0
for slave CPOL=1,CPOL=1

One side should send out data rising clock and sample incomming data on falling clock.
The other side should send out data on falling clock, and sample incomming data on rising clock.
Is that what you want?

Polarity and phase are important. Sampling the data on the wrong phase is a catastrophe, depending on what extra delays you have introduced in the transfer channel. If you don't have the required setup and hold times, you don't know what data the master or the slave or both of them will sample. Your LVDS chips might potentially delay your signals a bit, but have you verified how much it delays the signals, in relation to the cycle time of your 50MHz clock signal?

Another thing: If you send data to 48 slaves, all of them can hear the signal. But the 48 slaves will want to send data back at the same time, unless you explicitly change back that data signal into a tristated GPIO signal. So with all 48 slave-select inputs hard-coded - what do you use to select which of the slaves that will get any data routed into the MISO pin of the master?

You complain your master isn't receiving any data. But why should it? You have asked it not to. Unless, there is a timeout. But there will only be a timeout if you stop the master from sending. Or you deactivate all your slaves in some way.

Your main problem is: It doesn't work. That is a very strong indication that you need to backtrack a bit, and reconsider your assumptions. You have lots of things to think about. Every little assumption you have made should be matched to measurements and manual paragraphs.

Things like: do you want interrupts when you have data available? Or do you wait until you get a timeout or an overflow? How does your overflows affect your communication? Do you have the required settle and hold times? How does the slaves readjust to get into sync again if they get a spurious clock pulse? Or if one of them get a watchdog reset? How do you decide which slave data line will reach the master? And how do you make sure that the other 47 slaves does not destroy this signal?

But you could have connected that single master pin to every slave, in case you don't need two-way communication.

Or if you do need data from slaves, you use an additional gate and a couple of GPIO pins to specify an address, making sure that only one slave gets the enable signal.

You are basically building an elevator without sensors for floor position and top/bottom position. Then you let the elevator motor just count time to try to figure out if it is getting close to third or fourth floor, totally without feedback for error correction.

A SPI slave can work with constantly enabled slave select. But one single pulse extra or lost means it will be one bit off until you reset the controller or you deactivate/reactivate the slave-select signal. What mechanics do you have to get your slaves to know when to reset the SPI controller, since you obviously can't toggle the slave select input?

Where did you find the recommendation to use:

here i am using for master CPOL=0,CPHA=0
for slave CPOL=1,CPOL=1

One side should send out data rising clock and sample incomming data on falling clock.
The other side should send out data on falling clock, and sample incomming data on rising clock.
Is that what you want?

Polarity and phase are important. Sampling the data on the wrong phase is a catastrophe, depending on what extra delays you have introduced in the transfer channel. If you don't have the required setup and hold times, you don't know what data the master or the slave or both of them will sample. Your LVDS chips might potentially delay your signals a bit, but have you verified how much it delays the signals, in relation to the cycle time of your 50MHz clock signal?

Another thing: If you send data to 48 slaves, all of them can hear the signal. But the 48 slaves will want to send data back at the same time, unless you explicitly change back that data signal into a tristated GPIO signal. So with all 48 slave-select inputs hard-coded - what do you use to select which of the slaves that will get any data routed into the MISO pin of the master?

You complain your master isn't receiving any data. But why should it? You have asked it not to. Unless, there is a timeout. But there will only be a timeout if you stop the master from sending. Or you deactivate all your slaves in some way.

Your main problem is: It doesn't work. That is a very strong indication that you need to backtrack a bit, and reconsider your assumptions. You have lots of things to think about. Every little assumption you have made should be matched to measurements and manual paragraphs.

Things like: do you want interrupts when you have data available? Or do you wait until you get a timeout or an overflow? How does your overflows affect your communication? Do you have the required settle and hold times? How does the slaves readjust to get into sync again if they get a spurious clock pulse? Or if one of them get a watchdog reset? How do you decide which slave data line will reach the master? And how do you make sure that the other 47 slaves does not destroy this signal?