I have been through the USB sample code downloaded from the keil website and i have a few questions regarding how the endpoints are used
1) they have used a macro in the code to convert from logical endpoint number to endpoint address
#define IDX2EP(idx) ((((idx)<<7)&0x80)|(((idx)>>1)&0xF))
on working this out , i got a pattern of 0x00,0x80,0x01,0x81...0x0f,0x8f. How was this macro derived? There is nothing in the user manual about the actual addresses of endpoints.
2) Each of these addresses correspond to a memory location of 1 byte . Where do the incoming and outgoing packets go? there are variable packet sizes possible so i was under the assumption that the individual buffers for endpoints are of variable size . Where are these individual buffers located?
3) The code enables endpoints at 0x05 and 0x82 which correspond to logical endpoints 5 and 10. Why not 4 and 5 both of which correspond to logical endpoint 3 (4 is out and 5 is in) ? Does it make a difference which endpoint is enabled as long as it if of the required type (bulk/interrupt etc)?
4) I came across this macro
#define LE_WORD(x) ((x)&0xFF),((x)>>8)
I am not able to understand what it does. what does the comma mean? It was used at multiple locations. to get product and vendor ids, to get max packet size for an endpoint and also to get bcd USB value in device descriptor
thanks for your time.
www.beyondlogic.org/.../usb5.shtml
USB Descriptors
Endpoint Descriptors
Endpoint descriptors are used to describe endpoints other than endpoint zero. Endpoint zero is always assumed to be a control endpoint and is configured before any descriptors are even requested. The host will use the information returned from these descriptors to determine the bandwidth requirements of the bus.
Field: bEndpointAddress Description: Endpoint Address Bits 0..3b Endpoint Number. Bits 4..6b Reserved. Set to Zero Bits 7 Direction 0 = Out, 1 = In (Ignored for Control Endpoints)
NXP Semiconductors UM10211 Chapter 13: LPC23XX USB device controller Table 249. Fixed endpoint configuration
logical endpoints 5 : Bulk (Supposed to be Data Transfer) logical endpoints 10: Interrupt (Supposed to be Control) (I believe you need both Data Transfer and Control)
logical endpoint 3: Isochronous (Not enough, maybe not appropriate either)
http://www.keil.com/forum/16477/
Tsuneo Chinzei, 3-Mar-2010 12:10 GMT
The USB SIEs on NXP LPC family MCU classify each endpoint into interrupt/bulk/isoc (and default control) transfer type. Actually, these bulk and interrupt endpoints can be exchanged, because there is no difference on the handling of bulk and interrupt transaction of the device side. NXP calls double buffered endpoints as bulk, single buffer ones as interrupt.
NXP Semiconductors UM10211 Chapter 13: LPC23XX USB device controller
6.3 Endpoint RAM (EP_RAM) Each endpoint buffer is implemented as an SRAM based FIFO. The SRAM dedicated for this purpose is called the EP_RAM. Each realized endpoint has a reserved space in the EP_RAM. The total EP_RAM space required depends on the number of realized endpoints, the maximum packet size of the endpoint, and whether the endpoint supports double buffering.
2) Each of these addresses correspond to a memory location of 1 byte I don't understand this question.
-- Tired and frustrated. I will try to find a new job, I hope it is a position in Kaohsiung, Southern Taiwan.