Hi there, i've got a project realizing mc8051 on a FPGA board and using mon51 of keil uvision3 for debugging. I got my VHDL code implemented and tested the functionality, the UART interface of the MC is working correctly, memory space is also von neuman wired, but the communication between my MC and the keil uvision is always wrong. I used the baudrate 9600 for the mon51 program. Is there any way to look inside what is going on? I mean is there any way to see if the mon51 on the ROM of my MC is working and is receiving some data from uvision? p.s. i used a new setting for mon51. For example i changed the starting address of xdata and code, excuted the install-batch with proper parameter, and generated a new hex file for mon51 of keil uvision. But the keil uvision always seems to be working with the old mon51 setting. Why?
thanks & regards chris
Do you mean this:
www.xilinx.com/.../spartan-3e_board_and_kit_documentation.htm
" href= "http://bit.ly/pjmJp6">http://bit.ly/pjmJp6
Yes,exactly.
So have you looked on the Xilinx site for stuff about their JTAG support?
Oregano 8051: www.oregano.at/.../8051.html
"If you have any comments or questions regards our 8051 IP core please feel free to contact us. We also offer - commercial - support for using and/or adapting the 8051 IP core in your industrial FPGA/ASIC designs. Please contact us for more details!"
Have you contacted them?
Yes andrew, a lot of times. But they were apparently not interested in my project, i didn't even get a response.
Does the monitor use 8-bit uart or 9-bit uart?
Please read the manual: http://www.keil.com/support/man/docs/mon51/mon51_config.htm
Thanks, there is one thing i'm not clear. I have my monitor program place at 0x8000h, and xdata from 0x7f00h to 0x7fffh, and user program from 0x0000h to 0x7effh. Do i need to modify the MON_BANK.A51 file?