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Hi
I have an error that shows its ugly head now and then.... The µC I'm using is C8051F122.
When I debug I can locate the problem, but the bug does not show the same place in code all times.
What I see now is that when stepping over the following line:
SMB0CN = 0x44;
The register SMB0CN actually is set to 0xC4. This sets the BUSY bit in the register.
It can be resolved by removing the µC supply, but a RESET won't do. But after some time the problem shows again.....
Does anyone have an idea????
Best Regards....
Compiler optimisation?
"What will cause SMB0CN.7 to be set?"
Surely, the Datasheet must tell you that?!
Do you have any interrupts? Is an interrupt scribbling over your memory? Is your stck big enough?
Is your stck big enough?
I meant stack of course.
I have tried to use lower the optimisation with no luck. The problem is that I can not recreate the problem, so it is very hard to locate.
I have I2C interrupt enabled, but it should not change the memory content. I have tried to set a break point in the interrupt function and it does enter the function.
I guess the SMB0CN.7 bit is set to indicate if any device on the I2C line is trying to communicate, or?
Regarding the size of the stack, I'm not sure how to check if the size is large enough????
Could you plz help?
Please note that it does makes no difference if I perform a reset by pulling the reset pin low, or if I press reset in the IDE. I see that the µC is reset but it starts with an error code indicating that I2C communication with onboard EEPROM fails. But if I turn off the supply shortly, and then let the µC startup the problem is gone.
I'm trying to figure out what the difference is between resetting the µC and to power cycle it.
The only thing that I can come up with is that the EEPROM is also powered down during the power cycle, but I can't see what difference that can make....
The difference is that only one of these resets the I2C EEPROM, too. I2C can communication get stuck if you reset the master halfway through a transaction, and then just start a new one.
Hi Hans
That was my theory too. But I'm not sure what how to prevent that communication is stopped halfway....
Would it be enough to verify that the BUSY bit (SMB0CN.7) equals 0 (0=free, 1=busy)
But I'm not sure what how to prevent that communication is stopped halfway....
You quite probably can't. Reset will reset everying. Immediately. Software gets no say in what is stopped or not, once the CPU resets.
You'll have to reset I2C communication state in the slaves somehow...