This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

LPC2129 Port 0 Parrallel data - on no consecutive pins

Hello Friends,

I have to read 16-bit data from Port 0 of LPC2129.But the data is not available on consecutive pins.
So I assigned a name to each pin like PDB0. To read all 16 bits into a single byte I wrote the following macro to use in my code:

#define DigitalData1() (PDB0|PDB1<<1|PDB2<<2|PDB3<<3|PDB4<<4|PDB5<<5|PDB6<<6|PDB7<<7|PDB8<<8)
#define DigitalData2() (PDB9<<9|PDB10<<10|PDB11<<11|PDB12<<12|PDB13<<13|PDB14<<14|PDB15<<15)
#define DigitalData() ( DigitalData2() | DigitalData1())

I use DigitalData() to get the 16 bit word into a local variable like this:

ADC7606DataBuff = DigitalData();

Problem here is, this is eating good amount of time to process.

Can you suggest be what is the best way of coding to handle this kind of issues??

Thanks very much!

Parents
  • Please post documentation about what bits are available on what pins. Right now, we don't know your definition of PDB0, PDB1, ...

    Most probably, you can make a 32-bit read, and then extract groups of bits and group-shift or send through lookup tables.

    Having totally random bit orders, you can do:

    uint32_t map0[256] = { ... }
    uint32_t map1[256] = { ... }
    uint32_t map2[256] = { ... }
    uint32-t map3[256] = { ... }
    
    uint32_t tmp = value_from_port;
    uint32_t value = map0[tmp & 0xff] | map1[(tmp >> 8) & 0xff] | map2[(tmp >> 16) & 0xff] | map3[tmp >> 24];
    

    This wastes 4kB of flash space for the four lookup tables. The ((tmp >> 8) & 0xff) operation can also be replaced with an explicit 8-bit read, since many of the NXP ARM chips can read the ports as 1 32-bit register, 2 16-bit registers or 4 8-bit registers, so you get:

    uint32_t value = map0[port0_byte0] | map1[port0_byte1] | map2[port0_byte2] | map3[port0_byte3];
    

    If we know the true bit allocations, you may be able to just extract a couple of bit groups to shift left or right and merge - but we need to see in which order you mapped the pins.

Reply
  • Please post documentation about what bits are available on what pins. Right now, we don't know your definition of PDB0, PDB1, ...

    Most probably, you can make a 32-bit read, and then extract groups of bits and group-shift or send through lookup tables.

    Having totally random bit orders, you can do:

    uint32_t map0[256] = { ... }
    uint32_t map1[256] = { ... }
    uint32_t map2[256] = { ... }
    uint32-t map3[256] = { ... }
    
    uint32_t tmp = value_from_port;
    uint32_t value = map0[tmp & 0xff] | map1[(tmp >> 8) & 0xff] | map2[(tmp >> 16) & 0xff] | map3[tmp >> 24];
    

    This wastes 4kB of flash space for the four lookup tables. The ((tmp >> 8) & 0xff) operation can also be replaced with an explicit 8-bit read, since many of the NXP ARM chips can read the ports as 1 32-bit register, 2 16-bit registers or 4 8-bit registers, so you get:

    uint32_t value = map0[port0_byte0] | map1[port0_byte1] | map2[port0_byte2] | map3[port0_byte3];
    

    If we know the true bit allocations, you may be able to just extract a couple of bit groups to shift left or right and merge - but we need to see in which order you mapped the pins.

Children
  • Thanks mate, here is the order of pins mapping

    #define PDB0 (IO0PIN_bit.P0_0) /*P0.0 D0 */
    #define PDB1 (IO0PIN_bit.P0_1) /*P0.1 D1 */
    #define PDB2 (IO0PIN_bit.P0_2) /*P0.2 D2 */
    #define PDB3 (IO0PIN_bit.P0_3) /*P0.3 D3 */
    #define PDB4 (IO0PIN_bit.P0_11) /*P0.11 D4 */
    #define PDB5 (IO0PIN_bit.P0_12) /*P0.12 D5 */
    #define PDB6 (IO0PIN_bit.P0_13) /*P0.13 D6 */
    #define PDB7 (IO0PIN_bit.P0_15) /*P0.15 D7 */
    #define PDB8 (IO0PIN_bit.P0_16) /*P0.16 D8 */
    #define PDB9 (IO0PIN_bit.P0_22) /*P0.22 D9 */
    #define PDB10 (IO0PIN_bit.P0_21) /*P0.21 D10*/
    #define PDB11 (IO0PIN_bit.P0_23) /*P0.23 D11*/
    #define PDB12 (IO0PIN_bit.P0_24) /*P0.24 D12*/
    #define PDB13 (IO0PIN_bit.P0_29) /*P0.29 D13*/
    #define PDB14 (IO0PIN_bit.P0_28) /*P0.28 D14*/
    #define PDB15 (IO0PIN_bit.P0_30) /*P0.30 D15*/

    most of the pins are randomly placed..

  • Thanks mate, here is the order of pins mapping

    #define PDB0 (IO0PIN_bit.P0_0) /*P0.0 D0 */
    #define PDB1 (IO0PIN_bit.P0_1) /*P0.1 D1 */
    #define PDB2 (IO0PIN_bit.P0_2) /*P0.2 D2 */
    #define PDB3 (IO0PIN_bit.P0_3) /*P0.3 D3 */
    #define PDB4 (IO0PIN_bit.P0_11) /*P0.11 D4 */
    #define PDB5 (IO0PIN_bit.P0_12) /*P0.12 D5 */
    #define PDB6 (IO0PIN_bit.P0_13) /*P0.13 D6 */
    #define PDB7 (IO0PIN_bit.P0_15) /*P0.15 D7 */
    #define PDB8 (IO0PIN_bit.P0_16) /*P0.16 D8 */
    #define PDB9 (IO0PIN_bit.P0_22) /*P0.22 D9 */
    #define PDB10 (IO0PIN_bit.P0_21) /*P0.21 D10*/
    #define PDB11 (IO0PIN_bit.P0_23) /*P0.23 D11*/
    #define PDB12 (IO0PIN_bit.P0_24) /*P0.24 D12*/
    #define PDB13 (IO0PIN_bit.P0_29) /*P0.29 D13*/
    #define PDB14 (IO0PIN_bit.P0_28) /*P0.28 D14*/
    #define PDB15 (IO0PIN_bit.P0_30) /*P0.30 D15*/

    most of the pins are randomly placed..

  • Thanks mate, here is the order of pins mapping

    #define PDB0 (IO0PIN_bit.P0_0) /*P0.0 D0 */
    #define PDB1 (IO0PIN_bit.P0_1) /*P0.1 D1 */
    #define PDB2 (IO0PIN_bit.P0_2) /*P0.2 D2 */
    #define PDB3 (IO0PIN_bit.P0_3) /*P0.3 D3 */
    #define PDB4 (IO0PIN_bit.P0_11) /*P0.11 D4 */
    #define PDB5 (IO0PIN_bit.P0_12) /*P0.12 D5 */
    #define PDB6 (IO0PIN_bit.P0_13) /*P0.13 D6 */
    #define PDB7 (IO0PIN_bit.P0_15) /*P0.15 D7 */
    #define PDB8 (IO0PIN_bit.P0_16) /*P0.16 D8 */
    #define PDB9 (IO0PIN_bit.P0_22) /*P0.22 D9 */
    #define PDB10 (IO0PIN_bit.P0_21) /*P0.21 D10*/
    #define PDB11 (IO0PIN_bit.P0_23) /*P0.23 D11*/
    #define PDB12 (IO0PIN_bit.P0_24) /*P0.24 D12*/
    #define PDB13 (IO0PIN_bit.P0_29) /*P0.29 D13*/
    #define PDB14 (IO0PIN_bit.P0_28) /*P0.28 D14*/
    #define PDB15 (IO0PIN_bit.P0_30) /*P0.30 D15*/

    most of the pins are randomly placed..

  • Was a bit sad that you managed to get 9 different "ranges". Using the same pins on different order, you could have managed with 5 "ranges".

    Number of steps to shift left is:

    0: 0
    1: 0
    2: 0
    3: 0
    4: 7
    5: 7
    6: 7
    7: 8
    8: 8
    9: 13 <= should have been swapped with next
    10: 11
    11: 12
    12: 12
    13: 16 <= should have been swapped with next
    14: 14
    15: 15
    

    Alas, having 9 groups means that you need 9 groups of (inputs & mask_x) << shift_x.

    My four tables in previous post was to map 32 bits to 32 bits. You only need to map 32 bits into 16 bits, so you could get away with four tables of 256 short each, i.e. 2kB of flash space. That is the fastest way you can merge your port bits.

  • Hardware was already designed by someone. I am left with no option, expect finding a good way of writing some efficient programs, to reduce system overhead...