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hello i have an opcode of BNE branch which is 1AFFFFF9 and i want to know to which address go this branch i mean how i know what is the next address executed
yes i asked there but up till now i didn't know how can i determine the jump address and i ask here maybe i find a better answer
take a look at this code
000138: e92d40f0 stmdb sp!, {r4, r5, r6, r7, lr} 00013c: e1a07000 mov r7, r0 000140: e59f00bc ldr r0, [pc, #188] ; [000204] 000144: e1a06001 mov r6, r1 000148: e59f10b8 ldr r1, [pc, #184] ; [000208] "w" 00014c: eb00033e bl 000e4c(33e) 000150: e2505000 subs r5, r0, #0 ; 0x0 000154: 0a000027 beq 0001f8(27) ; jump
000158: e3560064 cmp r6, #100 ; 0x64 'd' 00015c: 1a000008 bne 000184(8) ; jump 000160: e59f40a4 ldr r4, [pc, #164] 000164: e1a00004 mov r0, r4 000168: eb000544 bl 001680(544) 00016c: e1a02000 mov r2, r0 000170: e1a00004 mov r0, r4 000174: e3a01001 mov r1, #1 ; 0x1 000178: e1a03005 mov r3, r5 00017c: eb000339 bl 000e68(339) 000180: ea000007 b 0001a4(7) ; jump
000184: e59f4084 ldr r4, [pc, #132] ; [000210]
look at this bne opcode 00015c: 1a000008 bne 000184(8) ; jump how they determine the jump address 000184
You already have a perfectly good answer!
If you want a better answer, you need to provide a better question which clearly explains what, exactly, you want to know and why, exactly, you can't understand the other answer.
Simply ignoring people who have taken time to answer your question is not a great way to endear others to help you...
Do you understand what an "Offset" means?
i didn't ignore any person if you think so i'm sorry Andy i asked in several forum maybe i find a good and easy explaination only.
about your quetion mirror.href.com/.../Segments.html
cmagical.blogspot.com/.../memory-cell-residence-memory.html
OK, so you found some pages that mention "Offset".
But do you actually understand what "offset" means?
BTW: those pages are using it in the specific context of the intel x86 - which is not relevant here...
the offset is an optional number which is added to the address base(address of memory location) for jump or go to a desired address.
Correct.
So how do you think that is applied in the case of a jump instruction?
What do you think is considered the "base" address in this context?
i didn't understant your quetions well
let's take the branch BNE ,its opcode is 1AFFFFF9 1 = Condition: not equal A = Branch (Link = 0 if =1 the curent address it will save in R14) offset = FFFFF9
You want to know what address the jump will jump to, don't you?
You have found that the FFFFF9 is an offset.
You know that an offset is applied to some "base" address to give a resulting address - how do you think that would be applied in the case of this branch instruction...?
It's time for you to do some thinking, rather than just wait for answers to be handed to you on a plate.
http://www.keil.com/support/man/docs/armasm/armasm_Cacdbfji.htm
do you mean how reach to the target address it is my quetion an i get the answer in the forum which you refer to it
Target Address = PC + 8 words(offset)
i want to ask you andy look at this assembly code
IF (a == b) AND (c == d) THEN e = e + 1; ------------- CMP r0,r1 Compare a and b CMPEQ r2,r3 If a == b THEN compare c and d ADDEQ r4,r4,#1 if c == d then increment e by 1
The next instruction, CMPEQ r2,r3,performs a comparison only if the result of the first line was true how the processor linked the first and the second and the third instruction with each other!
You really need to look a the instruction set a little more. Where is the EQ status bit set? The second line says compare R2,R3 AND the EQ status bit. The same with the third line. Add only if the EQ bit is 1. Remember, almost all insructions in the ARM can be conditional. Bradford
insructions--insructions-- instructions. Wish I could type. Bradford
thank you Bradford for your help
that's mean before the execution of The second instructon it must check the first instruction CMP r0,r1 (instruction set).
but up till now i don't understand the relation between the first and the second instruction can you give me an example
What do you mean by "relation" here?
As far as the CPU is concerned, it just executes instructions in order (until changed by some kind of branch or interrupt) - so there is no "relation" between instructions other than the order in which they appear in memory.
Unless you're thinking of some other meaning of "relation" here?
The order in which instructions appear in memory is determined by the programmer as the order needed to achieve the purpose of the program.
In the case of a High-Level Language (HLL), the compiler will synthesise the high-level operations with an appropriate sequence of low-level (machine) instructions.
Does that answer your question? If not, you need to explain the question more clearly...
A number of processors have support for conditional processing of instructions. That means that when they reach the instruction (in this case the second instruction), it checks a processor flag to decide if it should process the instruction or treat it as a NOP instruction and continue to the third instruction.
The second instruction in this case is only performing a comparison if the first instruction found a match.
The third instruction is also conditional. So it will only perform an ADD if the previous two instructions both compared equal. So the add only happens if instr1 arg1 == arg2 and instr2 arg1 == arg2.
If instruction 2 sees a difference, then both second and third instructions will be treated as "NOP" instructions. If first instruction matches, and second instruction sees a mismatch, then the third instruction will be treated as a "NOP".
So the only relation involved is that the conditional instructions will be processed or not, based on the result of previous instructions.