We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
Has anyone have code sample to demonstrate how to transfer 8 channel ADC into memory (ADCArray[8]).
I'm having issue with interrupt between ADC and DMA.
Is there way for interrupt to trigger DMA only if all 8 channels is completed (via burst mode).
Oh dearly me I forgot to mention this....it LPC1768.
Nothing there to explain how it generate interrupts signal when *all* channel is completed.
It generates interrupt when any one of ADC is completed (via masking). but there is no interrupt to say all channel is completed. It does not say it performs ADC channel in sequence?
I have read the LPC1768 manual and indeed helpful only for 1 channel but not many channel.
So what made you think that a feature like that is supposed to exist?
Such an advanced device and we're in year 2010, scanning all channel and then generates a signal to indicates the scan is completed with all ADC buffer updated ready for DMA, it seems pretty obvious hardware feature for multi-channel ADC and DMA while keeping Cortex free for other demanding task.
And it really didn't occur to you that a more appropriate question might have been "Can this chip do this", rather than your "Gimme sample code demonstrating how the chip does this"?
www.beyondlogic.org/.../usb1.htm
The USB host controllers have their own specifications. With USB 1.1, there were two Host Controller Interface Specifications, UHCI (Universal Host Controller Interface) developed by Intel which puts more of the burden on software (Microsoft) and allowing for cheaper hardware and the OHCI (Open Host Controller Interface) developed by Compaq, Microsoft and National Semiconductor which places more of the burden on hardware(Intel) and makes for simpler software. Typical hardware / software engineer relationship
Thank for discussion, I look other ICs elsewhere.
Fair enough.
But, this time, be sure to discuss your requirements with the vendor carefully & in detail to ensure that the part does what you require!
Will looking for other processors help?
We have seen none of your code. We have heard nothing about what you have attempted to do, what you expected to happend and what did happen.
Who is generating interrupts?
Have you disabled ADC DMA in NVIC as specified by the manual?
Have you configured single or bust DMA transfers?
The manual claims "The DMA transfer size determines when a DMA interrupt is generated. The transfer size can be set to the number of ADC channels being converted (see section 31-5.20)."