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Multiple ULINKs on one PC?

I was wondering if it is possible to have two [or more] ULINK devices running on the same PC ?

I 'expect' [hope] to be able to launch two Keil IDE's and run two Target Boards using two ULINK devices.

Is that possible?

Ref:
http://www.keil.com/forum/docs/thread6385.asp
(Noting that it went un-answered, and it is really old)

--Cpt. Vince Foster
2nd Cannon Place
Fort Marcy Park, VA

Parents
  • Tamir & Per: Thanks for the good info about NSS/SSEL lines.

    Per, I do realize those issues, but when the data-sheets say Hardware Controlled, then I'd expect it to be just that at least on a per-byte basis.

    They shouldn't advertize Hardware Control if it doesn't do that.

    And like PWM A/B signals, dead-time controls could be put into the fabric (ref#3).

    In cases of #2, I would expect it to be software controlled.

    Case #1 is simply some glue logic to chip-select which slave to address, and NSS/SSEL the enable (or AND gates) for each slave. ...which is what I had expected to do.

    I'm not shooting holes in your logic, its just that your conclusion might be valid (So it is quite complex), but it is definately possible and fairly easy to do in an FPGA/VHDL to address my "counter-points."

    At this point, we are most likely going to move the SPI bus into the FPGA to handle everything as we would like it, and simply memory map the data I/O. (We need speed).

    Again, thanks for the information. I'll definately keep your points in mind when we do move it into the FPGA.

    --Cpt. Vince Foster
    2nd Cannon Place
    Fort Marcy Park, VA

Reply
  • Tamir & Per: Thanks for the good info about NSS/SSEL lines.

    Per, I do realize those issues, but when the data-sheets say Hardware Controlled, then I'd expect it to be just that at least on a per-byte basis.

    They shouldn't advertize Hardware Control if it doesn't do that.

    And like PWM A/B signals, dead-time controls could be put into the fabric (ref#3).

    In cases of #2, I would expect it to be software controlled.

    Case #1 is simply some glue logic to chip-select which slave to address, and NSS/SSEL the enable (or AND gates) for each slave. ...which is what I had expected to do.

    I'm not shooting holes in your logic, its just that your conclusion might be valid (So it is quite complex), but it is definately possible and fairly easy to do in an FPGA/VHDL to address my "counter-points."

    At this point, we are most likely going to move the SPI bus into the FPGA to handle everything as we would like it, and simply memory map the data I/O. (We need speed).

    Again, thanks for the information. I'll definately keep your points in mind when we do move it into the FPGA.

    --Cpt. Vince Foster
    2nd Cannon Place
    Fort Marcy Park, VA

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