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[Cortex-M3] Library float point initialization generates busfault

Zypimeious Herectus

Hi,

I'm using Cortex-M3 and software float point.
During C library initialization ( before reach main ) the fp_init will generate a bus fault.

Bus fault is not generated when Microlib is used.

I'm using MDK-ARM 4.10.

Have anyone experienced this issue with FP before?

What could be wrong?

The only workaround right now is to use Microlib or remove FP usage.

Depending on how the float point C code is removed/manipulated it will generate fault at fsub, fnormalize and so on.

Parents
  • 0 in reply to Tamir Michael

    I haven't read the documentation for the LPC2478, but wouldn't be too surprised if it is similar to the LPC2378. A master can control many SPI slaves, which means a need for multiple slave-select lines in master mode.

    And not all SPI protocols toggles the slave-select between each word or between each burst. And different SPI slaves have different minimum requierments for the setup and hold times for the SS signal in ns or in relation to the clock frequency the SPI device is using.

    So why should NXP add an errata for the chip not doing something that they haven't said that it should do?

Reply
  • 0 in reply to Tamir Michael

    I haven't read the documentation for the LPC2478, but wouldn't be too surprised if it is similar to the LPC2378. A master can control many SPI slaves, which means a need for multiple slave-select lines in master mode.

    And not all SPI protocols toggles the slave-select between each word or between each burst. And different SPI slaves have different minimum requierments for the setup and hold times for the SS signal in ns or in relation to the clock frequency the SPI device is using.

    So why should NXP add an errata for the chip not doing something that they haven't said that it should do?

Children
  • 0 in reply to edPer Westermark

    Per,

    I agree, but this feature is not even mentioned in the user manual. So, the reason why "it does not work" remains obscure until a scope is connected to the bus to reveal that the chip select line remains high...

  • 0 in reply to Tamir Michael

    The things we find out The Hard Way. This time, I'm prepared for the NSS signal's odd behavior.

    Undocumented Features are always 'fun' when crunch time comes. One of the reasons to go with a FAST processor: to make it up by bit-banging.

        (1x) STM32F103xG (ARM Cortex M-3)
  + (1x) USB Hub (uPD720114)
  + (1x) Xilinx FPGA (XC3S400A)
  + (4x) Ti TMS320C2812 (DSPs)
  + (4x) Actel IGLOO Nano FPGAs (AGLN250V2)
 -------------------------------------
  = Sweet and fun times ahead... along with headaches + (x120) meds.

    --Cpt. Vince Foster
    2nd Cannon Place
    Fort Marcy Park, VA