Hello I have a problem related with uart & pc communication over Phytec Board. When I configure UART5 as parity disable, then the communication between uart5 & pc is successful. But when I configure UART5 as parity enable with even parity, then the communication between uart5 & pc becomes problematic. LSR interrupts generating, the last byte of a message is received as the first byte of the latter message that I have sent. I have only changed U5LCR register with EvenParity and ParityEnable. Is there anything that I have missed? Anyway, also I have changed the pc side as well.. Thank you