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Hi, how can I detect on what port (port 0 or 2) and pin (pin 0 to 31) a interrupt on EINT3 was genereted?
if (IO_INT_STAT & P0int) ...
if(IO_INT_STAT & P2int) ...
to figure out what port. But whats is P0int and P2int in this case? What bit to look for? I guess I check IO0_INT_STAT_F and IO2_INT_STAT_F in a simular way to find out what pin. What bits to look for and how do I translate them to pins? Any example of a ISR function that writes out port and pin would be great.
forgot to mention: Its a LPC2368
The EINT interrupts are a special form of interrupts, and (almost) completely separate from the pin-change interrupts.
For EINT interrupts, you normally install a separate interrupt handler for each of the EINTx pins you want to handle, with the special case that EINT3 shares VIC channel 17 with the GPIO interrupts.
You can check the IOIntStatus register to see if bit 0 (P0Int) or bit 2 (P2Int) is set - that means that you have pending pin-change interrupts from PORT0 or PORT2.
To then check exactly what pin(s) on PORT0 or PORT2 that trigged an interrupt, you have to continue the analys is as:
The IO0IntStatR register then tells if you have any pending rising edge interrupt for PORT0. Correspondingly IO2IntStatR handles PORT2.
IO0IntStatF tells if you have any pending falling edge interrupt for PORT0. Correspondingly IO2IntStatF handles PORT2.
In the same way, you can check the EXTINT register, bit 3, to see if you have a pending EINT3 interrupt.
So the ISR for VIC channel 17 can detect what pins that are trigged, and can service more than one. Obviously, the most time-critical interrupts should be routed to EINT0..EINT2 since they have dedicated VIC channels, removing the need to detect the source while also allowing you to program the individual priority for the different interrupt sources.
What about Port1? I cant find any IO1IntStatR or similar. How do I check for interupts on Port1?
How do I check for interupts on Port1?
On what basis do you assume that Port 1 has interrupt functionality in the first place?
Did you even try to read your chip's datasheet before asking here?
Isn't it enough if the processor can support up to 64 I/O pins with pin change interrupts?
I haven't had any troubles allocating pins requiring interrupts to either any of EINT0..EINT3 or any of the pins on P0 or P2.