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Hello everybody,
I'm trying to program an Actel 8051s core with Keil uVision3 for a ProASIC3 FPGA and I have some problems.
Keil device database just contains Actel core8051 (a licensed version), but Core8051s is a stripped down version that enables users to add their own peripherals via an APB bus. Actel documentation suggest just to change the header file Reg51.h with the core8051s registers, but it doesn't work.
I'm a noob with this matters, but I suspect that more Keil libraries must be changed in order to adapt core8051s for uVision. Does anyone know how to program this core with Keil??
Thank you!
Yes, the core8051s maps the peripherals into XDATA space starting from address 0xF000.
The simulator is ModelSim, a FPGA software tool that shows the core signals in data and address buses, or movx, write, read, etc. In my Modelsim simulation, GPIO addresses F090 and F0A0 should appear in core address bus, but they don´t. Now that I know that there are more microcontrollers that work in Keil with the same principle (memory mapped peripherals) I will check the HEX file generated by Keil to confirm that the correct instructions are read by the core.
"(memory mapped peripherals)"
The whole point of memory-mapping in any architecture (not just 8051) is that the CPU neither knows nor cares whether these are "real" memory accesses, or accesses to memory-mapped peripherals - the Address and Data bus operations are identical...