Hi,
I'm trying to perform DMA transfer from LPC3131 internal RAM to MCI port. MCI block got 32x32 Bits FIFOs, but I wish to perform 512 bytes transfer ideally without help of the CPU during the transfer.
Can I do this by programming main DMA controller and MCI DMA controller to perform a 512 bytes transfer. In other words does DMA controller is able to automatically manage FIFO of the MCI port ? Or maybe I can use companion channels to achieve quite the same behaviour ?
Best regards
I'm not sure for your specific chip, but for other NXP chips, the source-device FIFO isn't used when using DMA. The FIFO is there to give the main application or interrupts a bit of time to respond.
The DMA can respond instantly, clocked by arrival of data from the source device.
NXP normally have quite good documentation of what you can configure when setting up DMA transfers.
Thanks for reply, but in my case the FIFO is in the destination peripherial. I wish to tranfer from memory to peripherial. I think that in this case, destination FIFO are used even with DMA.
You must configure the DMA to use destination flow control. Then the destination peripherial will inform the DMA when it can accept more data. This is basically the same as when you manually wants to send 512 bytes to a device that has a 32x4 byte FIFO. You will have to poll the status bits of the device, to see if the FIFO has room for more data, or you will have to let the target device create an interrupt when the FIFO can accepts more data. In this case, you configure the DMA channel to poll the status of the destination device.
Thanks a lot, I will do that.