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Receive Data Available Interrupt Problem - URGENT

Aykut Birsen

Hi,

I have a problem that I have to urgently solve. I am using LPC3250. I want to handle the IRQ interrupt for the receive data.
I mean, when data comes to the receive fifos, I want to get an IRQ interrupt and handle the tasks.

I wrote the following codes to enable the interrupt:

 MIC_ER = 0x200; // enable uart5 interrupts
 UNIER  = 0x01;  // enable receive data available interrupt.
 UNFCR  = 0x06;  // reset the transmit and receive fifos
 UNLCR  = 0x00;  // Reset DLAB to 0.

However, when I proceed in main, the code suddenly goes to the irq handler, although no data comes to fifo. In continuously takes irq interrupt and never stops at all.
What may be the problem? Am I doing anything wrong in enabling bits?

I'll be very glad to hear from you. Thanks for your helps..

  • 0 in reply to ImPer Westermark

    Hi, I solved the problem finally. But still have a few questions.

    I disabled the MIC (Main Interrupt Controller). I only configured the Uart5 Interrupt register. (U5IER = 0x01). Now, I dont ever use any ISR, but the UART interrupt itself gives me the value. I poll the U5IIR register and see 0x04 there.

    But, if I wouldnt use the MIC, so why does it have UART interrupt bits? For all these times I thought that I would first set MIC (MIC_ER = 0x200) and then set U5IER. But, MIC is completely useless here..

    I am missing a point?

  • 0 in reply to Aykut Birsen

    Note that many processors are designed devices to be interrupt-driven or polled.

    If interrupt-driven or polled, you can check the status registers to see all interrupt sources that needs processing. If using interrupts, then the processor will automagically select the most prioritized interrupt to handle, and the interrupt handler can see if other interrupt sources needs processing, or not. With interrupts off, you can still let the main loop check which devices that should have generated an interrupt, if interrupts were allowed.

    In the case of the register you have problms with - maybe the least significant bit is only valid when polling. Maybe that bit gets automatically cleared when you enter the interrupt handler, since you already know that you have an interrupt from the UART. So maybe the ISR never need to check the first bit. But when using interrupts, the ISR just must process any interrupt reasons from the UART, unless you want to get yet another interrupt as soon as you return from the interrupt handler.