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All,
I am trying to track down a problem of some code that was written by an 'overseas' 3rd party (I will be nice and not state the country of origin).
This code uses a single timer set at a 1mS interrupt rate in order to determine if the SPI is still communicating externally with it's master. If no communications are detected the timer resets the SPI port, clears the interrupt, and jumps to the reset vector. The problem is: the SPI port remains dead until a power cycle is accomplished.
The obvious fix is to use the watchdog (which is what I will eventually do), but I would like to understand the why of why this does not work (yes, bad coding practice is the real reason)...
Since the code jumps to the reset vector this is what I have been able to analyze:
(1) Since this is not a true reset (ie: via watchdog) all hardware registers are not reset - problem potential here. (2) The jump to the reset vector was accomplished while in supervisor mode, so the privleged registers (ie: SP,etc) can be written. (3) The timer interrupt was cleared prior to making the jump to the reset vector, so all interrupts are still enabled. (4) Since this is not a true reset, all resident code can still execute (ie: interrupt handlers). (5) The startup code will reset all initialized data, registers, etc prior to jumping to program main(), effectively returning data to a power up state.
One reason I can currently come up with as to why the SPI is never functional after this occurs is that maybe an interrupt occurs while in the startup code (clearing a tracking variable or resetting the processor registers). But the interrupt would also inhibit the startup code until it was serviced. This potential cause is (probably) not the only reason for this issue, and why I am asking for your input(s).
Unfortunately, this board has no JTAG to connect so stepping through the code is not an option. I could write to the serial port - if it was connected, but it isnt. Right now I am trying to analyze my way through this code before using a 'hammer' approach to solving this problem.
What else am I missing in this analysis? Thanks.
>> My crystal ball tells me you are using an ARM Cortex-M based processor > > The processor is an ARM7 LPC2103, not stated because of lack of > perceived relevance (although in hindsight it probably is relevant - > my bad).
0001f2 bd30 POP {r4,r5,pc}
Then how can this be a legal exception return? On ARM7 cores, exceptions must be returned from in ARM state and this is a Thumb instruction.
>> In Cortex-M you can request a proper reset via software > > Warning: this is not true with all Cortex processors. I was just > working with a LPC1765 Cortex M3 and it has NO mechanism to do a > software reset.
All Cortex-M cores support this, but apparently NXP chose (or forgot?) to implement this feature. Well, at least they documented this rather annoying fact.
-- Marcus
Marcus,
I mistakenly copied the .asm code from another file I thought was from the right ISR. The actual entry and return is:
000000 e92d5fff PUSH {r0-r12,lr}
return:
000170 e8bd5fff POP {r0-r12,lr} 000174 e25ef004 SUBS pc,lr,#4
which is similar to what is posted on arm website:
0x00001c: LDMFD sp!,{r0-r4,r12,lr} 0x000020: SUBS pc,lr,#4
Thanks for catching this error.
I followed up with NXP be confirm this was not an error - it isnt.
Additionally, ARMs website added the following:
"The IRQHandler C function above must be compiled with armcc, however, C_int_handler() may be a C function compiled for ARM or Thumb. The linker can add any necessary ARM/Thumb interworking veneers to perform the change of state."