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how to simulate double clock mode of P89V51RD2?

I defined my own sfr FST for P89V51RD2 micro in the header file. when I set the EDC bit, the keil debugger does not show any increase in throughput i.e. it treats it as a classic 12-clocker whereas it should now operate as a 6-clocker.

I have seleted the right device in <options for target..> & freq is 11.0592MHz. Ofcourse I can set the freq as 2x there, but that's not what it should supposed to be.

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