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Hi,
I am trying to get timer interrupts every second and update a variable. I use timer0 and do the settings as follows:
TIMCLK_CTRL1 = 0x04; //enable timer0 clock T0CTCR = 0x00; //use as a timer T0TCR = 0x01; //enable timer T0PR = 12999999; //set timer frequency to 1hz T0MR0 = 8; //match register0 is set to 8 T0MCR = 0x03; //reset and give interrupt when match occurs MIC_ER = 0x10000; // enable timer0 interrupts
Then, I write my interrupt subroutine as follows:
STMFD sp!, {r0-r3, lr} LDR R3, =0x01 LDR R1, =0x40044000 STR R3, [R1] // interrupt cleared BL C_Irq_Handler LDMFD sp!, {r0-r3, pc}
Everything works fine but, I can only get the interrupts for once. I do the setting s to continuously get the interrupt but it goes into the interrupt only once.
What is wrong with this, I dont understand. I'd be grateful if anyone could help me.
I think the info while(1); is providing relates to the high speed timer, whereas the OP is asking for info on Timer#0.
I can't see any Keil examples that use any of the timers of the LPC3250 apart from the high speed one.
As it happens, I'm looking as something similar right now on the LPC3250; but a different problem. Using RL-ARM, I can get a periodic interrupt from Timer#0, until I call isr_evt_set, then no more high speed interrupts come through.
So I'm also (probably) doing something wrong. Will post again if I find anything.
You can take a look at examples here: ics.nxp.com/.../
it might help.
Thanks while(1);, I'm on that one already. No luck so far though :(
Hmmm,
I think I might have found a minor problem with the RL-ARM code for the LPC3250. Specifically, the function/macro OS_TFIRQ() in RTX_Config.C
Will do more checks and if confirmed, pass onto Keil support.
Coskun,
I can't see exactly what you have wrong. Your configuration looks correct, and what you are doing to acknowledge the interrupt looks correct.
Maybe you should concentrate on your interrupt service routine. Do you have any other interrupts enabled? Do they mis-behave?
You are correct it will be in the new MDK.
I found the solution!!
I was using r1, r2 and r3 in the interrupt subroutine. I started using r9 and r10 and now it is working.
I think r1, r2 are reserved registers and we cannot use them to clear the interrupts.
Thanks for you all..
what do you mean you "think". has the user manual told you that?! I don't know your chip, but if it is like the LPC24xx in register allocation, your argument is plain wrong!
I think you should re-examine your solution.
You preserve registers R0 to R3 in the ISR and those registers certainly CAN be used to release the source of the interrupt.
Hint: The function you call from your ISR (C_Irq_Handler), what registers do you think that might use? Were they being preserved in your original code? These questions would be specific to the ARM core (not specific to a particular ARM device) and the ABI.