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i'm writing a code of a 4 bit pulse width modulator with the following code
llibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity PWM is port(CLK : in std_logic; D : in std_logic_vector (3 downto 0); PWM : out std_logic); end PWM; architecture Behavioral of PWM is signal tmp : std_logic_vector(3 downto 0); signal up_down : std_logic; signal Oup : std_logic; signal TC : std_logic; begin process (CLK, TC, tmp) begin if (CLK'event and CLK = '1' and TC = '0') then if (up_down = '1') then tmp <= tmp + 1; elsif (up_down = '0') then tmp <= tmp - 1; end if; elsif (TC'event and TC = '1') then tmp <= D; Oup <= not Oup; PWM <= Oup; up_down <= Oup; elsif (tmp'event and tmp = "1111") then TC <= '1'; elsif (tmp'event and tmp = "0000") then TC <= '1'; end if; end process; end Behavioral;
but i keep getting the following error when viewing the RTL schematic
ERROR:Xst:2358 - "C:/Users/Mazen/Documents/VHDL Projects/First/PWM/PWM.vhd" line 45: Operands of <AND> are not of the same size.
any ideas ??
Keil? A VHDL product?
You have run off course. The link is here:
http://dev.null.org/
A quick re-write of your code turns into this:
llibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity PWM is port ( CLK : in std_logic; D : in std_logic_vector( 3 downto 0 ); PWM : out std_logic ); end PWM; architecture Behavioral of PWM is signal tmp : std_logic_vector( 3 downto 0 ); signal up_down : std_logic; signal Oup : std_logic; signal TC : std_logic; begin process( CLK, TC, tmp ) begin if( CLK'event and CLK = '1' and TC = '0' ) then if( up_down = '1' ) then tmp <= tmp + 1; elsif( up_down = '0' ) then tmp <= tmp - 1; end if; elsif( TC'event and TC = '1' ) then tmp <= D; Oup <= not Oup; PWM <= Oup; up_down <= Oup; elsif( tmp'event and tmp = "1111" ) then TC <= '1'; elsif( tmp'event and tmp = "0000" ) then TC <= '1'; end if; end process; end Behavioral;
Let me think about it a bit. But it could be in the tmp'event statement where it is looking for any transition in a single specific bit transistion of the array and then being 'AND'ed with the full array.
Its late here, and I don't want to build a special project in my Actel's Libero FPGA IDE to figure it out right now. (1AM EST---my kid's baseball game is at 9AM ... in 8 more hours).
(Yes, I know its not Keil, but it is an interesting question).
Does my 're-write' match your code?
--Cpt. Vince Foster 2nd Cannon Place Fort Marcy Park, VA
Again its late on a Sunday evening, but I wanted to know if my answer helped. (I'm too busy to actually vet it properly at the moment).