Hey.
I am trying to setup a communication line between to lpc2388, by using ssp0 (as spi), where I have 1 slave and 1 master.
When I send (master), a write to the fifo buffer (8x16 bits), and it work fine.
But when I try to read it (on the slave side) from the rx buffer, I only get 1 half of the "frame" (the same 4x16 bits is copied). I only get the whole frame the first time.
Has any had the same problem?
Best regards Soeren.
The receiver will issue a FIFO interrupt when the FIFO is (at least) half-full.
If you stop sending data, then the receiver will get a receiver timeout interrupt, to let you pick up any remaining words in the FIFO.
Are you checking for both these conditions in the ISR?
Hi.
Communication is only from master to slave, and it is up to the master to pick up all the data.
My ISR is beeing executed whed the buffer is half empty, which is working finde.
The problem is maybe master.
I did not write about master and slave, but about receiver, since both sides of a SPI transfer are both senders and receivers.
In your case, you ignore the transfers from slave to master. That is ok. But have you code that takes care of the receive timeout interrupt in your slave?