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SPI_EEPROM INTERFACE WITH LPC2114

pavan kumar

Hi all,

I had written a code to interface 25c160 (SPI EEPROM) with lpc2114. I used proteus for simulation. But when i was de-bugging my code in keil, S0SPDR register is not taking any values.I am not able to understand what went wrong....
I am attaching my code......
Please guide my way out....

pavan
pavannaidu.v@gmail.com

#include <lpc21xx.h>
#include "spi.h"

unsigned char rd[5];

void spi_init(void)
{
        PINSEL0 = 0X00005500;   //SELECTING SPI MODE
        S0SPCCR = 0X78;                 //100KHZ
    S0SPCR  = 0x20;                     //MASTER MODE WITH 8-BITS PER TRANSFER
        IODIR0  = 0x00000400;   //SET SSEL0 AS OUTPUT;
}


unsigned char spi_tx_rx(unsigned char val)
{
        IOCLR0 = 0X00000080;
        S0SPDR = val;
        while(!(S0SPSR & 0x80));
        S0SPSR = 0X00;
        return S0SPDR;
        IOSET0 = 0X00000080;
}

void spi_write_en(void)
{
         IOCLR0 = 0X00000080;
         spi_tx_rx(WREN);
         wait();
         IOSET0 = 0X00000080;
}
void spi_write(unsigned char *val)
{
        spi_write_en();

        spi_tx_rx(WRITE);
        spi_tx_rx(0X00);        //ADDRESS: HIGHER BYTE
        spi_tx_rx(0X00);        //ADDRESS: LOWER BYTE
        while(*val)
        {
                spi_tx_rx(*val++);
        }

        wait();
}

void spi_read()
{
        int i;

        spi_tx_rx(READ);
        spi_tx_rx(0X00);        //ADDRESS: HIGHER BYTE
        spi_tx_rx(0X00);        //ADDRESS: LOWER BYTE
        for(i=0;i<5;i++)
        {
                rd[i] = spi_tx_rx(0x00);
                wait();
        }


}
/*
void write(unsigned char *dataa)
{
        while(*dataa)
                spi_write(*dataa++);
}

void read(void)
{
        int i;
        spi_read();
        for(i=0;i<5;i++)
        {
                rd[i] = spi_read();
                wait();
        }
}
  */
void wait()
{
        int j;
        for(j=0;j<50000;j++);
}

Parents
  • 0 in reply to pavan kumar

    One note in the datasheet is:
    "A low-to-high transition on CS after a valid write
    sequence initiates an internal write cycle."

    Another is:
    "The read operation is terminated
    by raising the CS pin (Figure 3-1)."

    A third note:
    "After all eight bits of the instruction are ransmitted,
    the CS must be brought high to set the write
    enable latch. If the write operation is initiated immediately
    after the WREN instruction without CS being
    brought high, the data will not be written to the array
    because the write enable latch will not have been
    properly set."

    But back to my initial comment. If you get a spurious clock cycle, and don't toggle CS - how will you then get the chip to synchronize again, so that it knows which clock cycle that represents the transfer of the first bit of a command or address or data byte?

Reply
  • 0 in reply to pavan kumar

    One note in the datasheet is:
    "A low-to-high transition on CS after a valid write
    sequence initiates an internal write cycle."

    Another is:
    "The read operation is terminated
    by raising the CS pin (Figure 3-1)."

    A third note:
    "After all eight bits of the instruction are ransmitted,
    the CS must be brought high to set the write
    enable latch. If the write operation is initiated immediately
    after the WREN instruction without CS being
    brought high, the data will not be written to the array
    because the write enable latch will not have been
    properly set."

    But back to my initial comment. If you get a spurious clock cycle, and don't toggle CS - how will you then get the chip to synchronize again, so that it knows which clock cycle that represents the transfer of the first bit of a command or address or data byte?

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