I want to design my code space as two halves, one part is 48KB which is resident in RAM and the other part 16KB is dynamically swappable based on the operations 8051 is required to perform. How should I organize and build my code?
1.) I am guessing I will need to design my own dynamic code page loader. I have an indirect ability to write to code space RAM structure using an external h/w piece.
2.) The problem for me is how should I organize my code and build it in this case since, I can have several pages of swappable code? Should I build each of these swappable 16KB code as absolute-segment libraries and assign them the upper 16KB address space? How about the data segments for these swappable code? Do I need to limit the range there as well?
Any insight will be helpful. Thanks.
Is there a reason for you to use an 8051 processor for this? Have you spent any time reviewing other processor architectures?
Why do you need to run code from RAM? To be able to replace the code? In that case - why not use a chip where you may replace the code but store and run the code from flash?