I want to design my code space as two halves, one part is 48KB which is resident in RAM and the other part 16KB is dynamically swappable based on the operations 8051 is required to perform. How should I organize and build my code?
1.) I am guessing I will need to design my own dynamic code page loader. I have an indirect ability to write to code space RAM structure using an external h/w piece.
2.) The problem for me is how should I organize my code and build it in this case since, I can have several pages of swappable code? Should I build each of these swappable 16KB code as absolute-segment libraries and assign them the upper 16KB address space? How about the data segments for these swappable code? Do I need to limit the range there as well?
Any insight will be helpful. Thanks.
No, one fine day, we suddenly realised we were out of code space. :-)
I don't want to rub it in, but the upcoming generation of Cortex processors is going to have to up 1 MB internal flash space...! Our LPC2478 has 512KB, and even so, I had to increase the size of the application on my flavor of the product on the expense of a low level firmware layer (we have 3 components in each controller - bootloader, a firmware layer and an application) to accommodate extra functionality. I have seen at least one project so far that failed due to internal flash running out at a too advanced stage.