I want to design my code space as two halves, one part is 48KB which is resident in RAM and the other part 16KB is dynamically swappable based on the operations 8051 is required to perform. How should I organize and build my code?
1.) I am guessing I will need to design my own dynamic code page loader. I have an indirect ability to write to code space RAM structure using an external h/w piece.
2.) The problem for me is how should I organize my code and build it in this case since, I can have several pages of swappable code? Should I build each of these swappable 16KB code as absolute-segment libraries and assign them the upper 16KB address space? How about the data segments for these swappable code? Do I need to limit the range there as well?
Any insight will be helpful. Thanks.
Right. We have h/w hooks to download code from flash into a RAM structure before 8051 execution begins.
One option we are considering is to build code as multiple banks, but, have the h/w alias multiple bank addresses to the same RAM structure. Then, manage the "shared" code RAM from the resident code making sure the intended bank code is physically present in the shared RAM before it is called.
I know we are going over hoops to make it work. But, we are limited due to cost and schedule reasons for the current design. And, we have already optimized the C-code as much as we think is possible.
Why Not stay with Standard Banking The compiler support this directly.
Cannot add more RAM structures for cost reasons/margin.