I want to design my code space as two halves, one part is 48KB which is resident in RAM and the other part 16KB is dynamically swappable based on the operations 8051 is required to perform. How should I organize and build my code?
1.) I am guessing I will need to design my own dynamic code page loader. I have an indirect ability to write to code space RAM structure using an external h/w piece.
2.) The problem for me is how should I organize my code and build it in this case since, I can have several pages of swappable code? Should I build each of these swappable 16KB code as absolute-segment libraries and assign them the upper 16KB address space? How about the data segments for these swappable code? Do I need to limit the range there as well?
Any insight will be helpful. Thanks.
But your proposed "solution" sounds like it will be neither cheap nor quck to implement - if it can be made to work at all!
The fact of the matter is that you have long outgrown this processor!
Your immediate effort might be better spent in trying to reduce the size of the existing code - while you make an urgent start working on a re-design that can actually accommodate your requirements!
You might want to take advantage of the Huge memory module and startup code. Within that 'huge' memory model is the ability to bank-switch by setting port I/O to chip-enable (or a higher than the 16-bit address to the RAM) the memory bank in which you need to access. The lower 64K address space and map can stay the same, but the port I/O can swap which chip it needs to read/write from.
The problem then becomes working around the Harvard architecture. But since it is RAM, then you should be able to point to that lower portion of the chip and do a movx instruction.
I might be way off base, but that is what I was thinking as I read this thread.
--Cpt. Vince Foster 2nd Cannon Place Fort Marcy Park, VA