Is the operation below an atomic operation in a multitasking environment like RTX-51? If it is not, then what is supposed to do to make it an atomic one except using locking mechanisms?
void func() { int locVal = globalVal++; ... ... }
This example is irrelevant. It may be one instruction to load the value 5 into a register and a second instruction to store the value.
Or it may be one instruction to load the constant, a second instruction to compute the effective address of the variable (for example with some processors and stack-based variables) and a third instruction to store the value.
But it isn't the number of instructions that is important in real life.
Does it matter if you get an interrupt between en instruction to load a resgiter with the value 5 and an instruction to store the value? Not unless the interrupt destroys the register contents.
In your last example, the question is: If an interrupt or other task reads your variable - what value will be read? Will it be the old value, or the new value (5) or a broken mix? In this case the store of the new value is atomic so another thread or interrupt will either see the old or the new value. In this case you got a atomic assign even if the source code had multiple instructions.
Some processors have special instructions or instruction flag bits to "lock" the processor for one or more instructions - for example to allow two 16-bit stores to a 32-bit integer. This is similar to disabling interrupts, but with an automatic enable, and the program doesn't need to know if interrupts was enabled or disabled when processing the lock instruction or processing instructions with lock flags.
Some processors have special hardware to create atomic updates to specific memory addresses. For example an assign to 16-bit timer register may be implemented with a 16-bit latch that requires the program to make two 8-bit assigns in a specific order. One of the 8-bit assigns just gets cached in the latch while the next 8-bit assign performs a full 16-bit transfer. The same thing exists for larger processors too - for example for a 16-bit processor to assign 32-bit timer values.