UART Question

The answser to your question depends upon the specific chip you are using; therefore, without that information, it is impossible to answer!

The chip itself may not even have such a feature - in which case, you'd just have to program the delay yourself.

"if you transmit two characters with a time period too short between them, it doesn't work."

What doesn't work?
In what way does it "not work"?

In general, there is no minimum time between characters - the whole reason for having both a stop bit and a start bit is that it allows characters to be sent back-to-back with zero delay between them!

The answser to your question depends upon the specific chip you are using; therefore, without that information, it is impossible to answer!

The chip itself may not even have such a feature - in which case, you'd just have to program the delay yourself.

"if you transmit two characters with a time period too short between them, it doesn't work."

What doesn't work?
In what way does it "not work"?

In general, there is no minimum time between characters - the whole reason for having both a stop bit and a start bit is that it allows characters to be sent back-to-back with zero delay between them!

This is highly application specific.

Master to slave transport (BAUD rate) time
    +
slave response time (interrupt usually: isr)
    +
slave receive register retrieval time
    +
internal UART peripheral re-ready state time (usually one slave machine cycle)
    +
slave isr exit.
    +
Second Master to Slave cycle... (repeat as required)

If the slave is going to need to expect Master transmit bursts that are faster than the slave's per-'byte' capacity, then the slave's internal hardware must support Queued Serial Buffering. (a 'byte' can be more than the 8-bits due to the start-stop-parity, so that is why I put it in quotes).

Most don't, and if they do, it is typically only two 'bytes' deep if you are lucky... and if they do incorporate two, then they might as well do a Queued Buffer that is deeper.

If the slave isr handler itself takes longer than the inter-Master transmit times between two consecutive transmits, you'll need to do two things on the slave end: 1) make sure one of the first things it does is empty the slave's receive buffer so it is ready for the next incoming Master transmit while the slave is still processing the first transmit 'byte' within the slave's ISR handler, and 2) block the Master from transmitting more than two 'bytes' before the slave's ISR can complete its processes and re-enter it's serial ISR to acquire the second Master transmission.

This is one of the reasons the DTR (Data Terminal Ready) and CTS (Clear to Send) lines are added to the typical USART component so that hardware can meter the Master-Slave to an acceptable 'byte' transfer rate.

If there is no hardware hand-shaking (DTR/CTS/RTS/etc), and you don't know your slave's maximum transmit/receive capabilities, then you better contact the people who made the slave unit... assuming that this information is not in their specifications and communications protocol documentation.

The start-stop bits are for the internal UART state machine to 'know' when a full 'byte' has been transmitted (and to detect 'byte' level errors).

Usually each bit in the 'byte' is over-sampled by at least five times the bit-rate, and a majority vote is taken on it to determine if the incoming bit is high-or low (a 1 or 0). This process is done to allow for slightly different BAUD rates to still be capable of a serial data link. (You'll, see from time to time, the tolerance levels associated with different BAUD rates, and this is the reason for it... the over-sampling/majority-voting: with this information you can calculate the maximum intolerance to longer messages due to the slight differences).

[Sorry Andy...] The start-stop bits do not tell the Master if the Slave is still too busy to empty the receive buffer in time for the Master to send another 'byte'.

IF it is a Queued Buffer, then again, the internal peripheral's state machine would know when to push the new 'bytes' onto the FIFO due to the start-stop bits.

Or you could await Jack Sprat's response and get the real scoop.

--Cpt. Vince Foster
2nd Cannon Place
Fort Marcy Park, VA

"[Sorry Andy...] The start-stop bits do not tell the Master if the Slave is still too busy "

Of course not - I didn't mean to say that they did.

The point of the start & stop bits is to guarantee that there will always be a falling edge at the beginning of the start bit - without the need for any additional "idle time" between characters.