• State Not Answered
  • Locked Locked
  • Replies 7 replies
  • Subscribers 22 subscribers
  • Views 10271 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Atomic block - intterupts proof on cortex-M3

Lukas Nowak

Hi,

I'm looking for solution, how to make atomic execution block on Cortex-M3 uC. What is the best solution for this?

Best regards,
Lukas

Parents
  • 0 Arm Employee Badge in reply to ImPer Westermark

    On some processors, the disable interrupt function might take sometime to take effect. This is because the masking is done via control register accesses through the bus. (there could be wait state on the bus and the write operation could be buffered, and the interrupt controller might need a cycle to update to the new setting).

    On Cortex-M3, the interrupt mask registers are inside the processors (e.g. FAULTMASK, PRIMASK). As soon as PRIMASK/FAULTMASK/BASEPRI is set, the effect come immediately. So if you set the PRIMASK and the interrupt arrived at the same time, the interrupt will have to wait until the mask is cleared. To do this, the interrupt mask registers are accessible by CPS, MSR and MRS instructions only, for example:

       CPSID   i  ; Set PRIMASK, disable interrupts
   CPSIE   i  ; Clear PRIMASK, enable interrupts

   CPSID   f  ; Set FAULTMASK, disable interrupts & hard fault handler
   CPSIE   f  ; Clear FAULTMASK, enable interrupts &
              ; hard fault handler

    In C, the function

      __disable_irq() translate to
       CPSID i


    and

      __enable_irq() translate to
       CPSIE i

    These functions are also available for other ARM cores (e.g. ARM7TDMI). But instead of changing PRIMASK, __disable_irq change the "I" bit in CPSR.

Reply
  • 0 Arm Employee Badge in reply to ImPer Westermark

    On some processors, the disable interrupt function might take sometime to take effect. This is because the masking is done via control register accesses through the bus. (there could be wait state on the bus and the write operation could be buffered, and the interrupt controller might need a cycle to update to the new setting).

    On Cortex-M3, the interrupt mask registers are inside the processors (e.g. FAULTMASK, PRIMASK). As soon as PRIMASK/FAULTMASK/BASEPRI is set, the effect come immediately. So if you set the PRIMASK and the interrupt arrived at the same time, the interrupt will have to wait until the mask is cleared. To do this, the interrupt mask registers are accessible by CPS, MSR and MRS instructions only, for example:

       CPSID   i  ; Set PRIMASK, disable interrupts
   CPSIE   i  ; Clear PRIMASK, enable interrupts

   CPSID   f  ; Set FAULTMASK, disable interrupts & hard fault handler
   CPSIE   f  ; Clear FAULTMASK, enable interrupts &
              ; hard fault handler

    In C, the function

      __disable_irq() translate to
       CPSID i


    and

      __enable_irq() translate to
       CPSIE i

    These functions are also available for other ARM cores (e.g. ARM7TDMI). But instead of changing PRIMASK, __disable_irq change the "I" bit in CPSR.

Children
No data