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Hi, I'm using AT91SAM9260 in a printer design. I'm using RL-RTX operating system.Since AT91SAM9 contains I & D caches and MMU built-in I'd like to use it.But, all the examples provided by Keil for AT91SAM9 had enabled only I-cache. How can I use both the I and D caches and MMU? Can I use MMU with RL-RTX?
Please help me.
In theory, you can use MMU with any program. The question is more what you want to solve, and what will happen.
In this case, I would think that you have to modify the os_switch_tasks() function, to get the different tasks to run in their own address spaces. The bad part is that - I don't have the full source, so I may be wrong - the common data structures used by RTX will have to be accessible from all tasks, so you will not get full isolation.
You will also get a bit of problem with allocation functions, since the MMU works on a different abstraction level than the allocation function - RTX does not know that it should map/unmap memory regions to your individual threads.
In the end, it might be easier to use the MMU to just write-protect critical information from all threads, than trying to get isolation between individual threads.
> But, all the examples provided by Keil for AT91SAM9 had enabled only > I-cache.
This is because the D-cache can only work if the MMU is enabled.
> How can I use both the I and D caches and MMU?
First of all, read the relevant sections in the ARM926 TRM. You will find that in order to enable the MMU you will have to provide a L1 page table and have the TTB register (cp15,c2) point to it. See below.
> Can I use MMU with RL-RTX?
Of course. The question is rather: "Does RL-RTX make active use of the MMU, e.g. for task management?" This I couldn't answer.
If you provide a page table, make sure it doesn't interfere with RL-RTX (in case it actually uses the MMU).
An ARMv5 level 1 page table consists of 4096 entries (words, one per section). In a trivial situation (need MMU only to be able to turn on D-cache) you would provide a flat mapping, e.g. every virtual section maps to a physical section with the same address. Set section attributes (cacheable, bufferable, permissions) appropriately. This data structure could be stored in flash or RAM. For an MCU with little memory to work with, and an OS that doesn't actually use the MMU, the page table could stay in flash, since most of the translations will be held in the TLB (64+8 entries) anyway.
Regards Marcus http://www.doulos.com/arm/
Thanks for ur suggestions..