Hi I am having issues with voltage levels on pins p1.4-p1.7 on a seehau emulator with c51 pod. My target is NXP 8051 based CMOS microcontroller with 32 I/O Lines, 3 Timers/Counters, 6 Interrupts/4 Priority Levels, ROMless, 128 Bytes On-chip RAM.
Without the emulator, when I plug in the NXP microcontroller, and flashed eeprom, I get about 2.1-2.3V on those pins, and the target functions correclty. when I use the emulator those voltages are at 1.8V not wnough for target to function correclty. Im using the scope to measure them. Pod is setup for external crystal and internal power. Vcc is at 5.1v in both cases with emulator and with microcontroller/eeprom. Any ideas on where to start troubleshooting? I guess it might have something to do with jumper settings on that pod but the user guise is not that detailed.
I've made great experince on this matter during last weeks ;-((( Read the intel application note "designing with 80C51BH" The output stage is a three-values/current-limited/pull-up-circuit. It seems not to work the same on all product suppliers but, in any case it depends also upon your inizialsation phase sequence for the ports.
Basically you have up to a maximum (but it is typically lower) the 0.75mA if your output voltage is above 2V and max 0.075mA if the pin voltage is below around 1.4 V. The application Note describes the circuit operation. Swithcing is controlled by the output pin voltage. This feature is used to reduce pull-up current when externally you pull down the pin but also acts as a limitation on driving capability when you are driving external loads like a transistor instead of a mosfet.
Therefore you must be very carefull in designing circuits attached to the P1 port. Mainly if you are designing professional devices that must work reliably over a wide temperatur range. (my design is safety critical and over -55 to 125 degC so imagine the spread of values...;-))
If required could provide some more data in a future.
the belief that a 'high' from a standard '51 has any oomph has been the bane of many design attempts.