Hello all, I have just recovered my STR9 from a fatal startup crash due to invalid setting of the SCU_CLKCNTR. My PLL generates a 48 MHz clock, and the source of the problem was the APBDIV bit field: dividing RCLK (=48 MHz) by 2 (so that APB is fed by a 24 MHz clock) is presumably invalid. But why is that? I have re-read the clocks chapter in the reference guide, to no avail.
for those of you who don't care... :), if you try to run a STR9 at 48 or 96 MHz, must set the FMISEL bit in SCU_CLKCNTR to slow don't the flash. The simulator does not complain about it, even the hardware does not work (and you must perform a manual flash erase procedure, ouch...)