US_TIMEOUT and US_TXEND in same interrupt

AT91/ARM7TDMI. I have a question about dealing with status bits US_TIMEOUT and US_TXEND when they arrive very close together.

I'm using a standard Atmel/ARM IRQ_ENTRY, a handler, and standard IRQ_EXIT to process the AIC COM0 interrupt that either of these generate (see below)

If the interrupt has been originally generated by US_TXEND, but a US_TIMEOUT arrives after we have checked the status bit but before we call IRQ_EXIT, then (although my US_TIMEOUT bit does stay set) the interrupt does not fire again to process US_TIMEOUT. How can I best arrange that I either jump straight back in, or catch both in the same handler ?

The handler looks like :

[call IRQ_ENTRY]
{
        unsigned int status;
        status = COM0->US_CSR & COM0->US_IMR;
        if ( status & AT91C_US_ENDTX){
                // process end TX
        }
        if ( status & AT91C_US_TIMEOUT){
                // process end RX
        }
         // what if interrupt was generated by ENDTX but TIMEOUT is set by the hardware HERE ?
}
[call IRQ_EXIT]

IRQ entry and exit are currently :

    MACRO
    IRQ_ENTRY $reg
        ;- Adjust and save LR_irq in IRQ stack
            sub r14, r14, #4
            stmfd sp!, {r14}
        ;- Write in the IVR to support Protect Mode
        ;- No effect in Normal Mode
        ;- De-assert the NIRQ and clear the source in Protect Mode
        ldr r14, =AIC_BASE
        str r14, [r14, #AIC_IVR]
        ;- Save SPSR and r0 in IRQ stack
        mrs r14, SPSR
        stmfd sp!, {r0, r14}
        ;- Enable Interrupt and Switch in SYS Mode
        mrs r0, CPSR
        bic r0, r0, #I_BIT
        orr r0, r0, #ARM_MODE_SYS
        msr CPSR_c, r0
        ;- Save scratch/used registers and LR in User Stack
        IF "$reg" = ""
        stmfd sp!, { r1-r3, r12, r14}
        ELSE
        stmfd sp!, { r1-r3, $reg, r12, r14}
        ENDIF
        MEND

        MACRO
        IRQ_EXIT $reg
        ;- Restore scratch/used registers and LR from User Stack
        IF "$reg" = ""
        ldmia sp!, { r1-r3, r12, r14}
        ELSE
        ldmia sp!, { r1-r3, $reg, r12, r14}
        ENDIF
        ;- Disable Interrupt and switch back in IRQ mode
        mrs r0, CPSR
        bic r0, r0, #ARM_MODE_SYS
        orr r0, r0, #I_BIT:OR:ARM_MODE_IRQ
        msr CPSR_c, r0
        ;- Mark the End of Interrupt on the AIC
        ldr r0, =AIC_BASE
        str r0, [r0, #AIC_EOICR]
        ;- Restore SPSR_irq and r0 from IRQ stack
        ldmia sp!, {r0, r14}
        msr SPSR_cxsf, r14
        ;- Restore adjusted LR_irq from IRQ stack directly in the PC
        ldmia sp!, {pc}^
        MEND