Hi,
When programming the SDRAM configuration, I remark a difference between LPC23xx.H and the NXP user.manual.lpc24xx with the addresses of EMC_DYN_CFGn and EMC_DYN_RASCASn registers.
For example in LPC23xx.H, EMC_DYN_CFG1 is at address 0xFFE08140 and in NXP doc at address 0xFFE08120 !
Unfortunately, it seems logical that NXP doc is right.
EMC_DYN_CFGx and EMC_DYN_RASCASx definitions in LPC23xx.h are now corrected (will be included in next release of the tool chain).
Thanks for your quick replies.
Unfortunately, because we must be carefull and recompile every examples if necessary.