This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

8051 RISC or CISC?

Is 8051 a RISC processor or a CISC processor?

thank you
ece tech

Parents
  • although the actual number of instructions is quite small!

    Well, it's a common misconception that "RISC" has anything to do with the number of instructions or "how much work" a single instruction can do. (I know you know that, I'm just mentioning it for everyone, including the OP, who maybe don't know it yet).

    RISC systems can have amazingly powerful instructions (ARM, for example, has a "count leading zeros" instruction, and a variety of multiply-accumulate instructions, and conditional execution, and implicit bit-shifts ... so one instruction can do a _lot_ of work.).

    RISC refers to load-store architectures, where there's one set of instructions (with a variety of adressing modes) that moves data to and from the CPUs registers, and another set of instructions (which only address registers) that manipulate/process data in the CPUs registers.

    Since "data manipulation" instructions on the '51 can use lots of adressing modes (for example, an ADD can add a register, a direct byte, an indirect byte, or immediate data to a register), the '51 can be considered a CISC architecture.

Reply
  • although the actual number of instructions is quite small!

    Well, it's a common misconception that "RISC" has anything to do with the number of instructions or "how much work" a single instruction can do. (I know you know that, I'm just mentioning it for everyone, including the OP, who maybe don't know it yet).

    RISC systems can have amazingly powerful instructions (ARM, for example, has a "count leading zeros" instruction, and a variety of multiply-accumulate instructions, and conditional execution, and implicit bit-shifts ... so one instruction can do a _lot_ of work.).

    RISC refers to load-store architectures, where there's one set of instructions (with a variety of adressing modes) that moves data to and from the CPUs registers, and another set of instructions (which only address registers) that manipulate/process data in the CPUs registers.

    Since "data manipulation" instructions on the '51 can use lots of adressing modes (for example, an ADD can add a register, a direct byte, an indirect byte, or immediate data to a register), the '51 can be considered a CISC architecture.

Children