Hi, Good Day.
I am working on ARM7TDMI core processor from Analog Devices family (ADuC703x). I developed a preemptive scheduler on the same in ARM environment. The functionality of the same is fine and its working well. For the purpose of optimization, i migrated into thumb mode using Keil RV compiler option (by changing the code generation option to THUMB mode and the optimization level option to 3 in C/C++ tab of the target settings option).
After changing the settings my code size is reduced by 2 KB. But, the complete functionality of the software got changed.
Can anybody help me out to get out of this problem? Also, I would like to know why this kind of behavior is occurring... Please let me know your valuable suggesions.
Thanking you in anticipation, Ravi Kumar Desaraju.
A major difference is that FIQ is a privileged mode and user mode is not, which affects access to CPSR (user mode can only read it). Why do you plan to execute your scheduling code in user mode? You can of course adjust CPSR while in FIQ mode (as you can from every privileged mode), but why would you? also note that CPSR is not saved automatically if you do that to switch to another privileged mode.
Note: ------ "There are several ways to enter or leave the Thumb state properly. The usual method is via the Branch and Exchange (BX) instruction. See also Branch, Link, and Exchange (BLX) if you're using an ARM with version 5 architecture. During the branch, the CPU examines the least significant bit (LSb) of the destination address to determine the new state. Since all ARM instructions will align themselves on either a 32- or 16-bit boundary, the LSB of the address is not used in the branch directly. However, if the LSB is 1 when branching from ARM state, the processor switches to Thumb state before it begins executing from the new address; if 0 when branching from Thumb state, back to ARM state it goes."
Hi Michel,
Thanks for your response.
You mean to say, scheduler should be running in privileged mode (FIQ) and the tasks should run in User mode right?
Is there any way to switch the modes dynamically....? (i mean can we change the mode setting bits of the CPSR)
Why not run your scheduler in IRQ mode? You only have one FIQ source - are you sure you want to spend it on your scheduler? Basically, your tasks should not run in privileged mode - executing
SUBS PC, LR, #4
from IRQ mode should bring you to the right task assuming your LR is restored correctly. You can switch modes manually while in privileged mode by writing to CPSR. Changing modes while in user mode can only occur by an exception.
Note that FIQ is a privileged mode. But not the only one.
why not compile everything but the context switch code in THUMB, and only the context switch assembly in ARM?
I tried that option using compiler directive #pragma thumb
I converted whole "C" code into THUMB and the assembly code in ARM. Its working fine.
But my specific requirement for this project is THUMB mode with optimization level as 3.
I cannot help you further unless I see your code.
"But my specific requirement for this project is THUMB mode with optimization level as 3."
Exacly why?
to reduce the ROM/code size.....
to reduce the ROM/code size.....<p>
But what if the compiler generated smaller code at optimization level 2 ? Sometimes, the optimizer will do things that are actually counter-productive.
The IDE has a specific check-box for "Optimize for Time", but no corresponding "Optimize for Size".
Many compilers starts to generate larger code for the highest optimization levels, because a higher priority is given to speed. Unrolling small loops can give great speed improvements, at the cost of size.
Depending on cache architecture, many compilers also starts to use a larger align value for really high optimization levels.
I think that's an either-or thing. It optimizes for size by default, but will optimize for time if the user requests it. So a separate check-box for "Optimize for size" is not necessary.
It makes sense to use Thumb "as much as you can" to optimize for size.
on an ARM7TDMI you CANNOT run with thumb code exclusively, you must have SOME ARM code. It really cannot be done so don't try to.
That being said, I would assume that having working code is more important than the size. Because it is much easier to get a scheduler to work in ARM code than Thumb code, you should write you scheduler in ARM code. I would also write it to be run though the SWI execption handler. This will put you into a priviledge mode AND into ARM mode. When you return from this you can have the USER registers all set up/restored and return to either thumb or ARM mode directly, without using a BX instruction.
Robert,
you wrote
I would also write it to be run though the SWI execption handler. This will put you into a priviledge mode AND into ARM mode.
I thought that all exception code is executed in ARM, even if the non-exception code runs in thumb? it is possible to switch to thumb in the handler, of course.
Yes, all exception/interrupt code has to start in ARM mode, since the processor does not know anything about the code when entering the exception handler.
I think he is trying to say that an SWI handler is an easy way to get into priviledged mode and into ARM mode. No need to consume the FIQ handler.
Yes, All the exceptions must be written in ARM mode. While you exit from the exception, the statement (return) itself switches the control back to THUMB mode. No need to execute a branch exchange instruction again to switch back to THUMB mode. This I experimented in FIQ handler and IRQ handler. I think it is same for all exceptions.
Well, coming to running the scheduler with SWI, how sure you are maintaining the performance of your scheduler with in the tolerance range. My application is to execute few tasks on a specific timing interval/periodicity. That's why I opted for a FIQ (using timer interrupt).