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interfacing MAX1232 to at89c2051?

Hi ! How to interface(soft ware wise) MAX1232 to at89c2051?

Thanks in advance,
nag

Parents
  • As a power monitor:

    A voltage detector monitors VCC and holds the reset
    outputs (RST and RST) in their active states whenever
    VCC is below the selected 5% or 10% tolerance (4.62V
    or 4.37V, typically). To select the 5% level, connect
    TOL to ground. To select the 10% level, connect TOL to
    VCC. The reset outputs will remain in their active states until VCC has been continuously in-tolerance for a minimum of 250ms (the reset active time) to allow the power supply and μP to stabilize.
    The RST output both sinks and sources current, while
    the RST output, an open-drain MOSFET, sinks current
    only and must be pulled high.

    As a watchdog:

    The microprocessor drives the ST input with an
    input/output (I/O) line. The microprocessor must toggle
    the ST input within a set period (as determined by TD)
    to verify proper software execution. If a hardware or
    software failure keeps ST from toggling within the minimum timeout periodâ€"ST is activated only by falling
    edges (a high-to-low transition)â€"the MAX1232 reset
    outputs are forced to their active states for 250ms
    (Figure 2). This typically initiates the microprocessor’s power-up routine. If the interruption continues, new reset pulses are generated each timeout period until ST is strobed. The timeout period is determined by the TD input connection. This timeout period is typically 150ms with TD connected to GND, 600ms with TD floating, or 1200ms with TD connected to VCC.
    The software routine that strobes ST is critical. The
    code must be in a section of software that executes frequently enough so the time between toggles is less
    than the watchdog timeout period. One common technique
    controls the microprocessor I/O line from two
    sections of the program. The software might set the I/O
    line high while operating in the foreground mode, and
    set it low while in the background or interrupt mode. If both modes do not execute correctly, the watchdog
    timer issues reset pulses.

Reply
  • As a power monitor:

    A voltage detector monitors VCC and holds the reset
    outputs (RST and RST) in their active states whenever
    VCC is below the selected 5% or 10% tolerance (4.62V
    or 4.37V, typically). To select the 5% level, connect
    TOL to ground. To select the 10% level, connect TOL to
    VCC. The reset outputs will remain in their active states until VCC has been continuously in-tolerance for a minimum of 250ms (the reset active time) to allow the power supply and μP to stabilize.
    The RST output both sinks and sources current, while
    the RST output, an open-drain MOSFET, sinks current
    only and must be pulled high.

    As a watchdog:

    The microprocessor drives the ST input with an
    input/output (I/O) line. The microprocessor must toggle
    the ST input within a set period (as determined by TD)
    to verify proper software execution. If a hardware or
    software failure keeps ST from toggling within the minimum timeout periodâ€"ST is activated only by falling
    edges (a high-to-low transition)â€"the MAX1232 reset
    outputs are forced to their active states for 250ms
    (Figure 2). This typically initiates the microprocessor’s power-up routine. If the interruption continues, new reset pulses are generated each timeout period until ST is strobed. The timeout period is determined by the TD input connection. This timeout period is typically 150ms with TD connected to GND, 600ms with TD floating, or 1200ms with TD connected to VCC.
    The software routine that strobes ST is critical. The
    code must be in a section of software that executes frequently enough so the time between toggles is less
    than the watchdog timeout period. One common technique
    controls the microprocessor I/O line from two
    sections of the program. The software might set the I/O
    line high while operating in the foreground mode, and
    set it low while in the background or interrupt mode. If both modes do not execute correctly, the watchdog
    timer issues reset pulses.

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