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ISR Overhead - Keil options?

Hello,

I am using a MSC1210Y5 just for reference. My question is about the ISR overhead of saving all the registers and other details when the an ISR is called.

For example using sending 32 bytes with no SERIAL0 ISR off and just testing TI_0 in a while loop incomparison to the same TI_0 while loop with SERIAL ISR on is generating an additional dealy after each byte being sent as expected for the ISR overhead.

The SERIAL0 ISR has to be enabled as it can recieve data at any time. I have no problems with the functional operation (TX/RX similtaneous) currently apart from the unnecessary ISR overhead on TX when no RX occurs which is 99% of the operations. I can see from the debugger that a large number of registers and other locations are being pushed as expected because my code and variable use is 'medium' on the keil scale .

When this TX/RX overlap occurs the code is in a 'safe' place, that is variables are protected etc. COmpared to when the SERIAL ISR could occur in other areas of the code.

Is it possible to add some directives (only push register / variable 'x' etc) to the code for the 'safe' area to minimise the register PUSH/POP to reduce the overhead? or some other compilation configuration to reduce the register use?

I am currently running at optimization level 8, favour speed, with the other options off.

I wanted some conformation before I recode the 'safe' section in assembly if it is not possible.

Thanks,

Paul