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Hi, My name is bharath i am studying a article on watchdog timers, i am in the middle of the article in that it is given as:: A properly designed watchdog mechanism should, at the very least, catch events that hang the system. In electrically noisy environments, a power glitch may corrupt the program counter, stack pointer, or data in RAM.
I was unable to follow what that power glitch is? and how it is going to corrupt the program counter,stack pointeror data in the RAM..... I have search the internet to know about it but i could not follow it properly.. I will be thankful to you people if you can give me some idea about that.
thanks in advance ..........
It relies on the availability of a clock signal to see time
That's one of the things that makes a bad watchdog according to the article ... good ones don't.
When the oscillator on the processor is dead, you don't need an external watchdog. If it's broken, you need to service the board. If you have a latchup, the external watchdog are normally unable to isolate all voltages to let the latchup disengage.
A built-in watchdog do work even if it's oscillator gets a hickup. Also, some built-in watchdog solutions makes use of a separate RC oscillator.
The problem here is: how many times would a built-in watchdog fail to reset the chip, while an external would manage? Theory is one thing, but many of the situations that would affect a built-in watchdog would also make the chip unable to respond to an external reset. That is the reason why solutions built for extreme reliability are using several redundant modules that can be powered up/down independently. But that is a completely different concept than internal/external watchdog.