Hello,
This is a non-Keil specific question but since lots of folks familiar with the Fx2Lp seems to be hanging out here i'm hoping that someone might have an answer:
I'm using EP2 as an input endpoint that is automatically filled via the external slave FIFO. This pipe is transporting data from my hardware to the PC. I also need a generic command/status mechanism so i want to use EP6 and EP8 as OUT/IN endpoints respectively so the PC can send various command requests to the FX2. The FX2 will send back response messages over EP8. The problem now is that i don't seem to be able to reliably source packets under CPU control over EP8 while the SLAVE FIFO is being used for EP2.
To source packets i simply put data into the EP8FIFOBUF, set the EP8BCH:EP8BCL and write 08h into ENDPKTEND to send the packet to the host. The host sometimes receives the packet and sometimes not. When running the code in a loop (host command / status from FX2) i'm seeing a kind of random behavior (sometimes it works, sometimes not). I'm using SYNCDELAY between the register wites.
Can anyone tell me if it is even possible to source data over the "big" endpoints while another big endpoint is being serviced by the slave FIFO?
Thanks, /John.
As I said in above post, I've not seen such an interference with GPIF. It may be a difference of slave FIFO and GPIF. Anyway, I'm glad to hear your problem was fixed, cheers.
Tsuneo