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Hi,
Since FX2 does not have a watchdog timer, I am trying to simulate watchdog behavior using Timer 2 on chip.
The timer setup seems to be functional, but when I try to execute longjmp(), FX2 dies. Any future access to the chip will hang. In the debugger, when I try to execute longjmp(), I will loose the debug connection. Thee only way to get it back is to reset USB.
Is this because of longjmp() or some other thing that I don't know. If it is not appropriate to use longjmp, how can I simulate the watchdog behavior so that lockup in 8051 can be prevented.
Any comments are welcome,
Thanks,
zhongsheng
here is the pseudo code I am using:
void main() { // ReEnumeration setjmp(jmp_buf); // Hardware setup // Initialization while (1) { // interrupt handling } }
void ISR_Timer2 interrupt 5 { TR2 = 0; TF2 = 0; longjmp(jmp_buf, 3); }
1) the IE priority which allow an interrupt to interrupt another. 2) the "simultaneous event priority", I qoute "the bible" (my emphasis) If requests of the same [IE} priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence.
Erik
I think I know what you are saying.
WatchDog Timer interrupt (Timer 2, 0x002B): Assigned Priority: High Nature Priority: 6
USB Interrupt (0x0043): Assigned Priority: Low Nature Priority: 8
Apparently, Timer 2 interrupt has higher priority than USB interrupt in both assigned and nature priority level. However, I just don't understand why Timer 2 ISR was not invoked when Timer out condition has been reached. I assume Timer 2 count should continue even the firmware is hung.
is that they can be turned off by simple means.
In my opinion no watchdog that can be turned off by simple means qualify as a watchdog, simply because runaway code easily can effect the turnoff.
turned off by simple means: e.g. clearing a bit or byte - in your case e.g. IE or EA or ET2. turned off and still be a watchdog: e.g. a requirement if two specific consequtive writes.