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Hi, I have to design a circuit using AT89C51 with no hardware SPI and use it as SPI master. The SPI slave device I am using is AT89C2051 which is controlling the RTC chip DS1307 using I2C protocol. When ever a particular event occurs the AT89C2051 records the timing registers. These RTC registers need to read by the master controller that is AT89C51 from the slave AT89C2051 using SPI protocol.
So by basic doubt is whether can I use AT89C2051 slave without a hardware SPI. Can I implement the whole of the SPI protocol between Master and the slave using software SPI.
Raghu
It is trivial to implement a SPI master in software.
It is a lot harder to implement a SPI slave in software, since the slave must be fast enough to not miss individual bits.
What approximate baudrate do you need to be able to transfer the generated data?
Unless you are going to use long signal lines between the two chips, the easiest thing is to do emit the bits of each word transfer either in a loop or unrolled for the individual bits. Since SPI is clocked by a separate signal, you don't even have to worry about an interrupt arriving and increasing the length of a bit cycle.
you can get HW SPI for less than $1 (e.g. NXP LPC) is it worth the fight - and the likelyhood of timing errors - to try "the beast" of a SW SPI slave.
Erik
There are not too much problems with any timing errors for a SW-driven master. It is trivial to make sure it isn't too fast.
Unless large volumes of data needs to be transmitted, or the data arrives in bursts larger than the buffer size, a SW master will be fast enough for quite a lot of jobs. If it isn't, then it isn't unlikely that a '51 chip with hw SPI isn't fast enough either.
There is a huge difference between bit-banging a UART or a Dallas one-wire communication and bit-banging the master side of SPI, since there is a separate wire for the clock. Jitter time does not matter the slightest, as long as the transfer rate is fast enough that the sender side doesn't suffer from buffer overflow.
The amount of code to implement the master side of SPI is puny. It takes longer to look at the data sheets of an alternative uC than it takes to implement the few code lines and test them.
I agree, but what about the bit-banged slave. a bit-banged slave must stop whatever it is doing (time critical or not) to receieve tha data. Yes, you may be able with an inverter or two to make it a bit less time consuming using interrupts, but there will still bee some potential timing problems with the "do it NOW" requirements a bit-banged slave, by definition, must have.
Had it not been for the plethora of HW SPI derivatives there is, I might have gone into a more detailled discussion of the many problems with a bit-banged slave, but I consider it futile to 'fight' bit-bang for a slave when getting the chip from another corner of the drawer solves it in a breeze. There is no shortage of the other features you can find in HW SPI chips - and at < $1.
I missed that the OP was discussing bit-bagging for both master and slave side.
That would require the master to run _very_ slow to make sure no bits are lost in either direction.
By the way: How I hate when the blasted site complains about my email address - at the same time I can hear it bing, receiving mails... If Keil could just permanently mark an email OK - especially if it is an email address that I have managed to mail them from - and they have managed to mail me back on...
Thanks for your reply. I would like to know is there any micro controller which is cost effective and minimum number of pins such as AT89C2051 with hardware SPI to implement a slave on the device. Raghu.
look at NXP LPC9xx series sub $1 sub 30 pins
www.nxp.com/.../index.html