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PLL configuration and limits

I am trying to make an eval-board MCB2368 work at 19.968MHz. According to the user manual, 275<Fcco<550MHz. However, at the errata sheet version 1.1 for LPC2368 is said that the limit for Fcco is 290MHz. So, I realize we have the range 275<Fcco<290MHz for LPC2368.

The LPC2368 documentation says also that 1<N<256 and 1<M<32768.

To match my needs, I found the values N=125, M=1456 (for these values I got Fcco=279.552MHz), both inside the respect range.

My problem is that for any value of N bigger than 37 the PLL doesn't work.

Some one can explain me if I am doing something wrong or is it really missing information at LPC2300 documentation?

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  • Sorry, I would mean Cclk=19.968MHz.

    The eval-board MCB2368 has already a 12MHz oscilation crystal. So, FIN=12MHz.

    My values:
    M = 1456
    N = 125
    clk divider = 14

    Using the formula:
    FCCO = (2 × M × FIN) / N
    FCCO = (2 × 1456 × 12) / 125 = 279.552MHz
    Cclk = Fcco / (clk divider) = Fcco / 14 = 19.968MHz

    My problem:
    When N>37 PLL doesn't work. And I need N=125.

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  • Sorry, I would mean Cclk=19.968MHz.

    The eval-board MCB2368 has already a 12MHz oscilation crystal. So, FIN=12MHz.

    My values:
    M = 1456
    N = 125
    clk divider = 14

    Using the formula:
    FCCO = (2 × M × FIN) / N
    FCCO = (2 × 1456 × 12) / 125 = 279.552MHz
    Cclk = Fcco / (clk divider) = Fcco / 14 = 19.968MHz

    My problem:
    When N>37 PLL doesn't work. And I need N=125.

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