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Hi ! I'm trying to put a MSC1212Y5 in power down mode. Despite all I have tried, the uC continues to draw a current of about 0.2...0.3mA, like there is some internal block (analog or digital) that isn't turned off. I have already wasted 3 days, trying to solve the problem. Sometimes, I succeed to obtain a current of less than 1 uA, but this doesn't lasts too much (maybe minutes) and the current rises again to few hundreds of uA. Anyhow, the small current (under 1 uA) it is obtained only if I cut the analog VDD off. Otherwise (with AVDD = 4.5V) the current through the AVDD pin is 0.25mA with all analog blocks turned off. I have read all the application notes I have found: sbaa's, sbaaz's, sbyt's, errata's and so on...useless. Can somebody (please) help me, because I'm in a terrible lack of ideas and (what's the most important) TIME !
Dear Kevin, Thank you a lot for your time and help! You are perfectly right about the atitude one must have, but: *The watchdog is not involved; all registers regarding it, use the default values, since I'm not interested in a watch-dog reset. The uC is put in Power Down and must be waked only by a real-time clock (DS1337), at a programmed hour, by a hardware reset. *EWU deals only with sources that might wake the uC from IDLE, not from PD (RESET is the only signal which do this). *I've checked the analog current: if the AVDD pin is supplied, there is no chance to reduce the analog current bellow 250uA, even if all analog sections are off. The only way to get rid of this current is to cut off the AVDD (this practice is discussed in an application note regarding the reduction of power consumption of MSC's, as being an used but not recommended method; this is because (they say...) MSC's need to see a valid AVDD during RESET, so auxiliary circuits must be used to make a correct RESET sequence; I have tried this also: there is no sign that MSC would care about AVDD during RESET; viewed from outside, the behaviour is the same either the AVDD is ON or OFF during RESET. * PDCON was made either 0xFF and 0x7F: nothing changed. *By default, both digital and analog brownout detection is off. I have checked this in program mode, by issuing RR7E and RR7F: both HCR0 and HCR1 have the correct values (0xFF, as I remember...). *From a certain point further, nothing is silly but rather possible... So, the PCB is a four layers one; it is a practice I use for a long time: it might seem to be too expensive, but finally, it is not! The two inner layers are for GND and DVDD. The tracks are short, since every power pin is faned-out and uses the plane layers; the board itself is small: 60x60mm. *The phenomenon is not similar to a reset, since I don't see the uC is running the program. All I see is that after a while (1...5 minutes) the digital current rises from 1uA (or less) to 700-800uA, in about 30 seconds. Then, sometimes, after another 30 seconds, the current goes down back to 1uA. This is like "something" inside (like an input), goes from a state to another, by slowly moving through a "linear" functioning domain, in which the CMOS gate has both MOSFETS open. It is like something's floating... *The only "work-around" I have found is that if I issue a slightly negative voltage on AVDD pin after PD, the phenomenon ceases (or seems to...). So, for now, the AVDD is supplied through a diode (1N4148) that is paralleled with a 47uF capacitor. The cathode is at AVDD pin and the anode receives the 4.5V supply and is tyied to ground through a 10K resistor. The 4.5V supply is switched on and off by a CMOS transistor. So, when I turn the AVDD off, the capacitor provides an -0.3V (limited by internal protection diodes) on AVDD pin, for a while. *Now, if you REALLY want to talk about "silly" things, this is the right moment...I'm not a bit proud of this stupid method, but is the only one it worked (and I don't know for how long...) I kept an eye on the ampermeter and, for 30 minutes (at least), the consumption seems to be constant low. At this moment it is very clear for me that there is a problem with MSC in power down: or the documentation is incomplete, or there is a hardware problem (or both...) * It is a pitty that such a powerfull uC, so stable and flexible and small is put in a shadowed corner by some managerial (marketing) issues (as I guess). Waiting for your (or other's) inputs, Gratefully Yours, Adrian
It sounds like a problem you should discuss with a TI support engineer. Is it a known problem, and do they have a known work-around.
The manual said that the AVDD was required during reset. Is it just that AVDD must be there when the reset signal is released, or is the requirement that AVDD must be applied at the same time - or in a specific sequence - compared to VDD? Most chips with multiple voltage sources have requirements about max voltage on one supply pin with regard to other supply bins, requiring diodes between the voltages to limit the voltage differences during power-on.
Might you have damaged some part of the chip?
Another thing besides turning off everything before power-down: Have you tried to set all output pins and internal signals in a low-level state? If your problem really is a gate slowly changing fro a high level to a low level, you might be able to force that specific signal to low before power off. The problem is of course to try to find out if you can affect the problematic gates. A lot of gates in the internal sequence machines are not possible to directly influence :(
Dear Per, Thank you for your input. I'll try to answer to your questions: 1.If it is a known problem then it might benefits of a secret work-around since there are no errata dealing with it ! SBAS323 (revised in september 2005 from SBAZ001C) doesn't mention anything about this issue. The only (colateral) information is :" After a reset, bits IDAC0DIS and IDAC1DIS are set to 0, thus enabling IDAC0 and IDAC1. This behavior is not desired since the current DACs should be disabled after a reset. The proper default value for these two bits should be 1.". When I found it, all the sky went blue for me and I suddenlly relaxed: "so, that is!"...Well, it wasn't... 2.Words have value, so it is not recommended to waste them with explanations...When it comes to descriptions, the phrases are written in a "Nostradamus" manner: anyone is free to understand what it likes to. I have tried to keep AVDD at the same supply with DVDD, in order to be sure that RESET will find it right, either when active or afterwards. There is no influence on the further behaviour: there is no way to get a consumption under 250uA in the analog section of the uC (they say that if everything is off in this section, then the consumption from AVDD is under 100nA !). The only way to get rid of these 250uA is simply to turn off the AVDD (inspired from Alexander's Gordian Node :)). It is obvious that this leaves some parts unsupplied and this might "upset" something inside, but I have product to finish, I based the design on the datasheet specifications and, finally, I blew it ! I have had to do something... 3. I don't think so, but how knows? Anyhow, I made the other 4 sensors and the sollution proved to be reproductible...Until now... 4. I can't put everything in low state, since there are devices requiring high states, or inputs (like RXD0, or RXD1) which are driven by outputs. I couldn't spread three-state buffers all over the place, since there was a space limit (it should be a small sensor, not a factory...). But all port pins that supported low states during power-down were configured like this. I have followed the recommendations...Anyhow, this reffers to an eventual sittuation of shortenning some pins to ground; the behaviour is the same if you configure the port pins as CMOS-output and leave them high or low, or if you configure them as inputs and they are driven at correct low or high states. I am sure there is no input left floating or 8051-compatible driven low or written low. I have checked this for many days...
The only observation was that if I touched the floating AVDD pin (unsupplied), the DVDD current decreased. I have put the probe on the pin and saw what I expected to: a 50 Hz ripple, limitted around GND, at about +/- 300mV. Since putting AVDD at the correct voltage would yeld a consumption of 250uA, I thought that it might be useful to try suppling it with a negative voltage, as this might "unlatch" the "something" inside...(this is quite an academic kind of speaking...). It worked...but now I'm feelling like the researcher who cut the flea's legs, say it: "Jump!" and noted that "after <legoctomy> the flea is no longer hearing". Thanking you (and others) for your time, and waiting for suggestions, Gratefully Yours Adrian Moldovan