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Problem in accessing Data Memory using FVAR : Need HELP!!

Govinda Padaki

Hello!

We have a DS80C400 based system. We have a CPLD
which has chip-select based on some Address lines
and PCE0#. The CPLD uses RD# and WR# lines instead
of PSEN# and WR#.

We have configured the MCU to use PCE0-3# as PCE
lines (instead of I/O) and Address lines A16-A21 to
be generated automatically.

We are trying to access 0x100000 (A20 is HIGH) using
the FVAR(unsigned char, 0x100000). However, the PCE0# is not getting asserted (it is at HIGH always).

ANy solution in mind? Please contact me for further
info. Also, Thanks in Advance!!

Thanks & BR,
Govinda Padaki

  • 0

    Hello!

    Also, I needed help on FVAR. Does it generate a MOVX instruction? How many cycles are required for this?

    Thanks & BR,
    Govinda Padaki

  • 0 in reply to Govinda Padaki

    I don't know, but you could easily check by examining the generated assembler:
    http://www.keil.com/support/man/docs/c51/c51_code.htm

  • 0 in reply to Andy Neil

    I also don't know to what extent the Simulator supports this stuff - but have you checked and/or tried it...?

  • 0 in reply to Andy Neil

    FVAR is just a macro. See "absacc.h".

    #define FVAR(object, addr) (*((object volatile far *) (addr)))

    #define FVAR(object, addr) (*((object volatile far *) ((addr)+0x10000L)))

    So, typically the far access does invovle a MOVX instruction. The duration of that instruction depends on your variant and how you've programmed the CKCON register. Far access also has to do some additional work to set up the high-order address bits. If you're concerned about overall performance, rather than hardware-level physical access time, you'll need to take this time into account. The details depend on your hardware. You should be able to find the details in the XBANKING.A51 or L51_BANK.A51 that you customized to match your hardware.

  • 0 in reply to Drew Davis

    Hi,

    Drew is right concerning the macros for FVAR.

    As for access on the DS80C400, assuming you use the 'typical' external memory access of this CPU, you will not need to worry about any 'extra' time'.

    Assuming you choose to use the Dallas C libraries (and why not, they're free and reasonably good), you will have the hardware configured for 24 bit memory access, so a FAR memory access is as efficient as an XDATA one.

    You should not have to worry about, or look at, the XBANKING.A51 or L51_BANK.A51 files.