hi all, I am Kirti Patel from india. i am using AT91RM9200+FPGA SBC board made by darell harmon... in this board when i read the status of the pio pins during execution ..at that time i am not getting the good response as on the pins.i.e.wrong response.and if i made changes through key pad to this particular pins at that time i did't get good response.... now in addition to this i want to start FPGA working on this board and send bitstream file through ARM9 controller.
so what i have to do??can any one help me about my problem.. Thanks.
This is a list of the registers associated with a GPIO port to review for how they are configured and handled at runtime:
PIO_PER PIO_PDR PIO_PSR PIO_OER PIO_ODR PIO_OSR PIO_IFER PIO_IFDR PIO_IFSR PIO_SODR PIO_CODR PIO_ODSR PIO_PDSR PIO_IER PIO_IDR PIO_IMR PIO_ISR PIO_MDER PIO_MDDR PIO_MDSR PIO_PUDR PIO_PUER PIO_PUSR PIO_ASR PIO_BSR PIO_ABSR PIO_OWER PIO_OWDR PIO_OWSR
Here are the steps I use in my AT91RM9200 bootloader to pump a bitstream into a Xilinx FPGA:
hi deny, i had done the same procedure as u wrote to me. but still in this procedure the DONE pin of the fpga doesn't go high..and INIT pin remains HIGH after sending bitstream file. so is it CRC error?? if yes then how it can be solved.?? THANKS.
"in this procedure the DONE pin of the fpga doesn't go high..and INIT pin remains HIGH after sending bitstream file. so is it CRC error??"
I don't have the Xilinx documentation in front of me at the moment, but as I recall, INIT does not indicate CRC error until after DONE goes high. I seems that there are other aspects of your load procedure that the device is unhappy with. Are you loading the bits in the correct order?
My procedure clocks bits most-significant bit first from a binary image created by a utility that I wrote which takes a .exo file (an FPGA configuration bitstream in Exormacs format [S-record]) and performs a bit reversal on each S-record data byte before storing the byte in the binary image.