ADC1256 not responding

You better start!

Give us hints what tests you have been performing. Does your fpga have correct programming? Is your read/write commands reaching the individual ADC? Are all signal pins on the ADC driven as they should? Can you write to the ADC?

"I am using 8 ADS1256 adc's in a board and through FPGA reading the output to microcontroller on multiplexing basis"

As Per says, you have far too many unknowns here!

Start simple: can you get your code to read a single ADC with no FPGA, multiplexing, or other stuff to confuse the issue?!

Are you using a real 80C251 chip, or is it a "soft" core within the FPGA?

Is it really a '251, or is actually just a '51 or '52?

Especially if it's a "soft" core, are you sure that the processor itself is correctly configured and working?
eg, have you done the basic LED flash and "Hello, World"?

initially i am just trying to read the configuration registers of the ADC.
But every time it gives a different output
sometimes it shows the values of five status register as 20 , 01 ,20 ,f0, E1
and next time other random values.
can I find some simple option of a Low noise ADC (communicating through SPI) which is not as erratic as this one.
even if i give inputs at its input pin the output is always faulty. ADc inputs are reaching ADC pin in a proper way that I have checked on oscilloscope.
Actually I wanted to knoe the proceedure of giving right commands to this ADC. Like when to reset it when to give synch signal etc.

"can I find some simple option of a Low noise ADC (communicating through SPI) which is not as erratic as this one."

Unless you actually have a broken chip, this will not be the fault of the ADC itself; it must be something in your system: analogue hardware and/or digital hardware and/or software...

"sometimes it shows the values of five status register as 20 , 01 ,20 ,f0, E1 and next time other random values"
How are you viewing those values?
How are you sure that it's the "wrong" values being read from the chip, rather than some problem in the way you view the values?

You said you have 8 multiplexed ADCs - maybe your multiplexing is broken, and you're reading different values from different ADCs...
As I said before, have you tried this on a simple system with no FPGA and only one ADC?

"Actually I wanted to knoe the proceedure of giving right commands to this ADC. Like when to reset it when to give synch signal etc."

Surely, that will be in the Datasheet?!
You certainly need to get the fundamentals like this sorted out before you start messing with FPGAs, multiplexing, and other such stuff!!

You still haven't answered the previous questions:

Are you using a real 80C251 chip, or is it a "soft" core within the FPGA?

Is it really a '251, or is actually just a '51 or '52?

Especially if it's a "soft" core, are you sure that the processor itself is correctly configured and working?
eg, have you done the basic LED flash and "Hello, World"?

It is best to always press "reply" on the last post in a thread, or it will soon be impossible to read the thread - this forum can not display a thread as a tree of posts.

can I find some simple option of a Low noise ADC (communicating through SPI) which is not as erratic as this one.

I am pretty sure that the ADC you are using is not erratic. I am pretty sure that you are doing something wrong. You have an oscilloscope. Have you checked that the signals from the fpga to the ADC looks reasonable when you try to access it? Have you checked that the timing is correct, so you don't try to communicate too fast?

The data sheet for the ADC contains information about timing and sequence for the different signals when you read from and write to the ADC. There is no use to continue with other work, until you have verified that you are not violating the requirements specified in the data sheet.

"There is no use to continue with other work, until you have verified that you are not violating the requirements specified in the data sheet."

Absolutely - and start with one ADC connected direct to the processor;

When you have that working, confirm that it still works with one ADC connected via the FPGA on one fixed channel;

When you have that working, confirm that it still works with one ADC connected via the FPGA on each of the other channels - still using one fixed channel at a time;

etc, etc,...

microcontroller is not soft core.
it's a hard core microcontroller.

in datasheet it is not given while reading or writing to status registers we have to give reset command or not. actually the board is already designed i cannot start from basic , like taking one ADC at a time , then check and all that. if the ADC is not having any problem and if I can view the input going at input pin why not the output is coming. According to datasheets the timing considerations I have taken care of.

before pointing to the ADC we have checked the FPGA programs and other sources from where fault may be caused.

sorry for I again forgot to reply to the last thread .
next time I will take care.

"actually the board is already designed i cannot start from basic , like taking one ADC at a time"

You don't have to do it on the real target board - set up a test rig with (an) evaluation board(s) or similar.

Manufacturer's product page: focus.ti.com/.../ads1256.html

Datasheet: www.ti.com/.../ads1256

Evaluation Module: focus.ti.com/.../ads1256evm.html

"in datasheet it is not given while reading or writing to status registers we have to give reset command or not."

If the datasheet doesn't mention it, why would you assume that it would be necessary?

This is what the datasheet says about RESET:

"On reset, the configuration registers are initialized to their default state..."

So what would be the point in writing to a register and then resetting the chip?

Wrong values are read from the chip because we are seeing the output signal coming from ADC output pin on the oscilloscope.
Input to the ADC is given correctly which we have seen on the oscilloscope with
120ns setup time
and 127ns hold time.

one more thing we have noticed is that on power up even when CLKIN is high and no other pin is having any other clock but still the D0/CLKOUT pin shows a clock of 16MHz clock, which is same as the system clock present for the microcontroller.

DRDY period doesn't changes according to the data rate,
sometimes it changes and sometimes it doesn't.
for example when we made data rate as 30Ksps and 15 ksps the DRDY period was same that was 60us.
and when we changed it to 1 KSPS DRDY period changed.
Clock input I am giving as 4.2 MHz.

Can it be possible because of not providing proper ESD protection the chip got damaged?

The analog side of a 24bit ADC is far more likely to be damaged by ESD than the backend computer interface.

If D0/CLKOUT/DRDY are signals that are expected to be driven by the ADC, have you made sure that it is infact the ADC that are driving them, so the FPGA doesn't do something weird?

Without looking in your data sheet: Is DRDY a signal that should change based on the baudrate, or is it a signal that should change whenever a new sample has been converted and is possible to read? If the second, then the DRDY frequency should normally not be affected by the baudrate.

d0 clkout is not connected to FPGA so no chance of driving that pin by FPGA
And regarding drdy, signal on power up it shows a periodic signal of particular period depending on the data rate .
Why it is like that I don't know