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Hi,
have this problem, using KEIL demo CA51's compiller KIT I'm trying to program my TUSB3410 that has 8052 core. This device is pre-programmed with a bootloader that downloads source code from HOST PC via USB and executes it in its RAM. Bootloader is for the whole enumeration process and downloading my microcode to its RAM, than it releases control to program downloaded to RAM. I'm making simple program that makes my diode twinkle on port P3.0. Here's an example:
#include "reg52.h" #include "types.h" #include "watchdog.h" #include "TUSB3410.h" sbit LED1 = P3 ^ 0; void delay( byte time) { BYTE i,j,k; for(i = 0 ; i < time ; i++) for(j = 0 ; j < 230 ; j++) for(k = 0 ; k < 230 ; k++); } VOID main(VOID) { DISABLE_WATCHDOG; while(1) { LED1 = 0; delay( 5); LED1 = 1; delay( 5); } }
and what is strange, it is obvious that i'll have there "jump" instructions 'cause I'm making some loops. I remind of my code beeing executed in RAM, so linker has to take care and add offset to jump instruction's destination address because this code will be placed in RAM not ROM. Bootloader will download my code to RAM, but if there's a jump instruction it's destination address must be fixed with ROM's lenght offset to avoid ProgCounter jumping to ROM areas. I believe it is arranged by choosing in KEIL the Target DEVICE as TUSB3410 and setting option in linker's menu: USE MEMORY LAYOUT FROM TARGET DIALOG. Everything works fine, diode twinkles, but if I change TARGET DEVICE to other TUSB device with different ROM space - after compilation my program is still working properly. If somebody has some experience with program code being executed in RAM and did something in KEIL and uVision IDE, will appreciate any help and explaination why is that. And if Sb have idea how to configure this properly i'll be grateful.
Cyrul
"linker has to take care and add offset to jump instruction's destination address because this code will be placed in RAM not ROM"
The 8051 doesn't work like that: the 8051 knows only CODE and XDATA address spaces - it is entirely irrelevant to the 8051 whether the CODE space contains ROM or RAM. See my post titled "Terminology" (23-Mar-2007 06:07) in this thread: http://www.keil.com/forum/docs/thread9542.asp
As ninja Z says, "After the loading, the RAM then got mapped into the CODE space, from 0x0000 on"
The 8051 has no instruction to write to CODE space - therefore the RAM must be mapped to XDATA space during the download; The 8051 cannot execute from anything other than CODE space - therefore the RAM must be mapped to CODE space to run the downloaded code.
"but if there's a jump instruction it's destination address must be fixed with ROM's lenght offset"
Yes: if there was a jump, that would be true true - but there isn't a jump instruction, so it's not!
"if Sb have idea how to configure this"
What does Antimony (Sb) have to do with this?!