Hi! I hope you can help me with this. I have a 8051 C146 Error in the uvision keil compiler inside Silicon labs IDE. The error is *** ERROR C146 IN LINE 320 OF C8051F020.H: 'P4' invalid base address The line of code giving the error is: sbit InputTrayCoverSen =P4^0; I think I have the P74Out setup right and P4 is 0x84. It is almost like Port 4 oesn't even exist or get recognized by the assembler. I have looked through your support webages and cannot even find this error C146 is not invalid base address. C166 is. I'm a bit confused. The entire code segments and setups are below: Many Thanks if you can help with this problem in any way! Richard Howes Continuing Engineering Manager 702-358-5714 /*--------------------------------------------------------------------------- ; ; ; ; ; FILE NAME : C8051F020.H ; TARGET MCUs : C8051F020, 'F021, 'F022, 'F023 ; DESCRIPTION : Register/bit definitions for the C8051F02x product family. ; ; REVISION 1.1 ; ;---------------------------------------------------------------------------*/ #ifndef __REGISTERS #define __REGISTERS /* BYTE Registers */ sfr P0 = 0x80; /* PORT 0 */ sfr SP = 0x81; /* STACK POINTER */ sfr DPL = 0x82; /* DATA POINTER - LOW BYTE */ sfr DPH = 0x83; /* DATA POINTER - HIGH BYTE */ sfr P4 = 0x84; /* PORT 4 */ sfr P5 = 0x85; /* PORT 5 */ sfr P6 = 0x86; /* PORT 6 */ sfr PCON = 0x87; /* POWER CONTROL */ sfr TCON = 0x88; /* TIMER CONTROL */ sfr TMOD = 0x89; /* TIMER MODE */ sfr TL0 = 0x8A; /* TIMER 0 - LOW BYTE */ sfr TL1 = 0x8B; /* TIMER 1 - LOW BYTE */ sfr TH0 = 0x8C; /* TIMER 0 - HIGH BYTE */ sfr TH1 = 0x8D; /* TIMER 1 - HIGH BYTE */ sfr CKCON = 0x8E; /* CLOCK CONTROL */ sfr PSCTL = 0x8F; /* PROGRAM STORE R/W CONTROL */ sfr P1 = 0x90; /* PORT 1 */ sfr TMR3CN = 0x91; /* TIMER 3 CONTROL */ sfr TMR3RLL = 0x92; /* TIMER 3 RELOAD REGISTER - LOW BYTE */ sfr TMR3RLH = 0x93; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */ sfr TMR3L = 0x94; /* TIMER 3 - LOW BYTE */ sfr TMR3H = 0x95; /* TIMER 3 - HIGH BYTE */ sfr P7 = 0x96; /* PORT 7 */ sfr SCON0 = 0x98; /* SERIAL PORT 0 CONTROL */ sfr SBUF0 = 0x99; /* SERIAL PORT 0 BUFFER */ sfr SPI0CFG = 0x9A; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */ sfr SPI0DAT = 0x9B; /* SERIAL PERIPHERAL INTERFACE 0 DATA */ sfr ADC1 = 0x9C; /* ADC 1 DATA */ sfr SPI0CKR = 0x9D; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */ sfr CPT0CN = 0x9E; /* COMPARATOR 0 CONTROL */ sfr CPT1CN = 0x9F; /* COMPARATOR 1 CONTROL */ sfr P2 = 0xA0; /* PORT 2 */ sfr EMI0TC = 0xA1; /* EMIF TIMING CONTROL */ sfr EMI0CF = 0xA3; /* EXTERNAL MEMORY INTERFACE (EMIF) CONFIGURATION */ sfr P0MDOUT = 0xA4; /* PORT 0 OUTPUT MODE CONFIGURATION */ sfr P1MDOUT = 0xA5; /* PORT 1 OUTPUT MODE CONFIGURATION */ sfr P2MDOUT = 0xA6; /* PORT 2 OUTPUT MODE CONFIGURATION */ sfr P3MDOUT = 0xA7; /* PORT 3 OUTPUT MODE CONFIGURATION */ sfr IE = 0xA8; /* INTERRUPT ENABLE */ sfr SADDR0 = 0xA9; /* SERIAL PORT 0 SLAVE ADDRESS */ sfr ADC1CN = 0xAA; /* ADC 1 CONTROL */ sfr ADC1CF = 0xAB; /* ADC 1 ANALOG MUX CONFIGURATION */ sfr AMX1SL = 0xAC; /* ADC 1 ANALOG MUX CHANNEL SELECT */ sfr P3IF = 0xAD; /* PORT 3 EXTERNAL INTERRUPT FLAGS */ sfr SADEN1 = 0xAE; /* SERIAL PORT 1 SLAVE ADDRESS MASK */ sfr EMI0CN = 0xAF; /* EXTERNAL MEMORY INTERFACE CONTROL */ sfr P3 = 0xB0; /* PORT